<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25448">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cavium: Clean uart code<br><br>* Don't init uart1 in bootblock.<br>* Allow UART init with zero baudrate.<br>* Init UART0..3 on Cavium's cn8100_sff_evb to fix kernel panic.<br><br>Tested on CN8100_SFF_EVB.<br><br>Change-Id: I1043b30318ec6210e2dd6b7ac313a41171d37f55<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/mainboard/cavium/cn8100_sff_evb/bootblock.c<br>M src/mainboard/cavium/cn8100_sff_evb/mainboard.c<br>M src/soc/cavium/cn81xx/uart.c<br>3 files changed, 16 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/25448/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c</span><br><span>index 4fe6e43..dcc9c90 100644</span><br><span>--- a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c</span><br><span>+++ b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c</span><br><span>@@ -16,8 +16,6 @@</span><br><span> if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {</span><br><span> if (!uart_is_enabled(0))</span><br><span> uart_setup(0, CONFIG_TTYS0_BAUD);</span><br><span style="color: hsl(0, 100%, 40%);">- if (!uart_is_enabled(1))</span><br><span style="color: hsl(0, 100%, 40%);">- uart_setup(0, CONFIG_TTYS0_BAUD);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c</span><br><span>index cc23cb5..b2b98dd 100644</span><br><span>--- a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c</span><br><span>+++ b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c</span><br><span>@@ -15,10 +15,17 @@</span><br><span> */</span><br><span> </span><br><span> #include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/uart.h></span><br><span> </span><br><span> static void mainboard_init(device_t dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- /* FIXME: stub */</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Init UARTs */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < 4; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!uart_is_enabled(i))</span><br><span style="color: hsl(120, 100%, 40%);">+ uart_setup(i, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span> static void mainboard_enable(device_t dev)</span><br><span>diff --git a/src/soc/cavium/cn81xx/uart.c b/src/soc/cavium/cn81xx/uart.c</span><br><span>index b3cce8e..e2d0157 100644</span><br><span>--- a/src/soc/cavium/cn81xx/uart.c</span><br><span>+++ b/src/soc/cavium/cn81xx/uart.c</span><br><span>@@ -225,6 +225,14 @@</span><br><span> write64(&uart->uctl_ctl, ctl.u);</span><br><span> </span><br><span> /**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Exit here if the UART is not going to be used in coreboot.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The previous initialization steps are sufficient to make the Linux</span><br><span style="color: hsl(120, 100%, 40%);">+ * kernel not panic.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!baudrate)</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /**</span><br><span> * 7. Initialize the integer and fractional baud rate divider registers</span><br><span> * UARTIBRD and UARTFBRD as follows:</span><br><span> * a. Baud Rate Divisor = UARTCLK/(16xBaud Rate) = BRDI + BRDF</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25448">change 25448</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25448"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1043b30318ec6210e2dd6b7ac313a41171d37f55 </div>
<div style="display:none"> Gerrit-Change-Number: 25448 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>