<p>Julien Viard de Galbert has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25440">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/denverton_ns: Implement AES-NI Lock<br><br>Change-Id: I6cf3484e46eebd3dc753d0903ea8555712b99b7e<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>---<br>M src/soc/intel/denverton_ns/cpu.c<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>2 files changed, 9 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/25440/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c</span><br><span>index ede4dae..d22cc58 100644</span><br><span>--- a/src/soc/intel/denverton_ns/cpu.c</span><br><span>+++ b/src/soc/intel/denverton_ns/cpu.c</span><br><span>@@ -107,6 +107,13 @@</span><br><span>      msr.lo |= FAST_STRINGS_ENABLE_BIT;</span><br><span>   wrmsr(IA32_MISC_ENABLE, msr);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+     /* Lock AES-NI only if supported */</span><br><span style="color: hsl(120, 100%, 40%);">+   if (cpuid_ecx(1) & (1 << 25)) {</span><br><span style="color: hsl(120, 100%, 40%);">+             msr = rdmsr(MSR_FEATURE_CONFIG);</span><br><span style="color: hsl(120, 100%, 40%);">+              msr.lo |= FEATURE_CONFIG_LOCK;          /* Lock AES-NI */</span><br><span style="color: hsl(120, 100%, 40%);">+             wrmsr(MSR_FEATURE_CONFIG, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+       }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>  /* Enable Turbo */</span><br><span>   enable_turbo();</span><br><span> </span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index 05ccc65..cc2e26e 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -29,6 +29,8 @@</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_PMG_IO_CAPTURE_BASE 0xe4</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span style="color: hsl(120, 100%, 40%);">+#define   FEATURE_CONFIG_RESERVED_MASK     0x3ULL</span><br><span style="color: hsl(120, 100%, 40%);">+#define   FEATURE_CONFIG_LOCK   (1 << 0)</span><br><span> #define IA32_MCG_CAP                  0x179</span><br><span> #define  IA32_MCG_CAP_COUNT_MASK       0xff</span><br><span> #define  IA32_MCG_CAP_CTL_P_BIT         8</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25440">change 25440</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25440"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6cf3484e46eebd3dc753d0903ea8555712b99b7e </div>
<div style="display:none"> Gerrit-Change-Number: 25440 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>