<p>Julien Viard de Galbert has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25426">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/denverton: Enable common block PMC<br><br>Mainly updating headers to build.<br><br>Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>---<br>M src/soc/intel/common/block/pmc/pmclib.c<br>M src/soc/intel/denverton_ns/Kconfig<br>M src/soc/intel/denverton_ns/acpi.c<br>M src/soc/intel/denverton_ns/include/soc/iomap.h<br>M src/soc/intel/denverton_ns/include/soc/pm.h<br>M src/soc/intel/denverton_ns/include/soc/pmc.h<br>M src/soc/intel/denverton_ns/pmutil.c<br>7 files changed, 28 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/25426/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>index cf87d05..6492248 100644</span><br><span>--- a/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>+++ b/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>@@ -454,6 +454,7 @@</span><br><span> return ps->prev_sleep_state;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef ETR</span><br><span> /*</span><br><span> * If possible, lock 0xcf9. Once the register is locked, it can't be changed.</span><br><span> * This lock is reset on cold boot, hard reset, soft reset and Sx.</span><br><span>@@ -486,6 +487,7 @@</span><br><span> reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;</span><br><span> write32((void *)etr, reg);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> </span><br><span> int vboot_platform_is_resuming(void)</span><br><span> {</span><br><span>diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig</span><br><span>index 35296d5..303b1e5 100644</span><br><span>--- a/src/soc/intel/denverton_ns/Kconfig</span><br><span>+++ b/src/soc/intel/denverton_ns/Kconfig</span><br><span>@@ -46,6 +46,8 @@</span><br><span> select SMP</span><br><span> select SOC_INTEL_COMMON_BLOCK</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_PMC</span><br><span style="color: hsl(120, 100%, 40%);">+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES</span><br><span> # select SOC_INTEL_COMMON_BLOCK_SA</span><br><span> select SOC_INTEL_COMMON_BLOCK_FAST_SPI</span><br><span> select SOC_INTEL_COMMON_BLOCK_GPIO</span><br><span>diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c</span><br><span>index 7386db3..433d611 100644</span><br><span>--- a/src/soc/intel/denverton_ns/acpi.c</span><br><span>+++ b/src/soc/intel/denverton_ns/acpi.c</span><br><span>@@ -129,7 +129,7 @@</span><br><span> fadt->pm1b_cnt_blk = 0x0;</span><br><span> fadt->pm2_cnt_blk = pmbase + PM2_CNT;</span><br><span> fadt->pm_tmr_blk = pmbase + PM1_TMR;</span><br><span style="color: hsl(0, 100%, 40%);">- fadt->gpe0_blk = pmbase + GPE0_STS;</span><br><span style="color: hsl(120, 100%, 40%);">+ fadt->gpe0_blk = pmbase + GPE0_STS(0);</span><br><span> fadt->gpe1_blk = 0;</span><br><span> </span><br><span> /* Control Registers - Length */</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h</span><br><span>index 29b231f..a7548d4 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/iomap.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/iomap.h</span><br><span>@@ -29,6 +29,7 @@</span><br><span> /* Southbridge internal device IO BARs (Set to match FSP settings) */</span><br><span> #define DEFAULT_PMBASE 0x1800</span><br><span> #define DEFAULT_ACPI_BASE DEFAULT_PMBASE</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_BASE_ADDRESS DEFAULT_PMBASE</span><br><span> #define DEFAULT_TCO_BASE 0x400</span><br><span> </span><br><span> /* Southbridge internal device MEM BARs (Set to match FSP settings) */</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h</span><br><span>index 2dc8781..5978b3a 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/pm.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/pm.h</span><br><span>@@ -20,10 +20,10 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <soc/pmc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define SLEEP_STATE_S0 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define SLEEP_STATE_S3 3</span><br><span style="color: hsl(0, 100%, 40%);">-#define SLEEP_STATE_S5 5</span><br><span style="color: hsl(120, 100%, 40%);">+/* TODO: Check that */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_MAX 127</span><br><span> </span><br><span> struct chipset_power_state {</span><br><span> uint16_t pm1_sts;</span><br><span>@@ -31,8 +31,8 @@</span><br><span> uint32_t pm1_cnt;</span><br><span> uint16_t tco1_sts;</span><br><span> uint16_t tco2_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe0_sts[4];</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe0_en[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_sts[GPE0_REG_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en[GPE0_REG_MAX];</span><br><span> uint32_t gen_pmcon_a;</span><br><span> uint32_t gen_pmcon_b;</span><br><span> uint32_t gblrst_cause[2];</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h</span><br><span>index edb5c55..4db3981 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/pmc.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/pmc.h</span><br><span>@@ -120,7 +120,10 @@</span><br><span> #define GPE_CTRL 0x40</span><br><span> #define SWGPE_CTRL (1 << 17)</span><br><span> #define PM2_CNT 0x50</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPE0_STS 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_REG_MAX 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_REG_SIZE 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_STS(x) (0x80 + (x * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_STD 0</span><br><span> #define GPIO31_STS (1 << 31)</span><br><span> #define GPIO30_STS (1 << 30)</span><br><span> #define GPIO29_STS (1 << 29)</span><br><span>@@ -166,7 +169,7 @@</span><br><span> #define IE_SCI_STS (1 << 3)</span><br><span> #define SWGPE_STS (1 << 2)</span><br><span> #define HOT_PLUG_STS (1 << 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPE0_EN 0x90</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_EN(x) (0x90 + (x * 4))</span><br><span> #define GPIO31_EN (1 << 31)</span><br><span> #define GPIO30_EN (1 << 30)</span><br><span> #define GPIO29_EN (1 << 29)</span><br><span>@@ -236,6 +239,12 @@</span><br><span> #define TCO2_CNT 0x0a</span><br><span> #define TCO_TMR 0x12</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory mapped IO registers behind PMC_BASE_ADDRESS */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PRSTS 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_GPE_CFG 0x120</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DWX_MASK 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_DW_SHIFT(x) (4 + 4*(x))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* I/O ports */</span><br><span> #define RST_CNT 0xcf9</span><br><span> #define FULL_RST (1 << 3)</span><br><span>diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c</span><br><span>index 542997c..6eb7db8 100644</span><br><span>--- a/src/soc/intel/denverton_ns/pmutil.c</span><br><span>+++ b/src/soc/intel/denverton_ns/pmutil.c</span><br><span>@@ -189,17 +189,17 @@</span><br><span> void enable_gpe(uint32_t mask)</span><br><span> {</span><br><span> uint16_t pmbase = get_pmbase();</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN));</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));</span><br><span> gpe0_en |= mask;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN));</span><br><span style="color: hsl(120, 100%, 40%);">+ outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));</span><br><span> }</span><br><span> </span><br><span> void disable_gpe(uint32_t mask)</span><br><span> {</span><br><span> uint16_t pmbase = get_pmbase();</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN));</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));</span><br><span> gpe0_en &= ~mask;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN));</span><br><span style="color: hsl(120, 100%, 40%);">+ outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));</span><br><span> }</span><br><span> </span><br><span> void disable_all_gpe(void) { disable_gpe(~0); }</span><br><span>@@ -207,8 +207,8 @@</span><br><span> static uint32_t reset_gpe_status(void)</span><br><span> {</span><br><span> uint16_t pmbase = get_pmbase();</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS));</span><br><span style="color: hsl(0, 100%, 40%);">- outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS));</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD)));</span><br><span style="color: hsl(120, 100%, 40%);">+ outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD)));</span><br><span> return gpe_sts;</span><br><span> }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25426">change 25426</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25426"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd </div>
<div style="display:none"> Gerrit-Change-Number: 25426 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>