<p>Julien Viard de Galbert has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25446">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/denverton_ns: Generate ACPI DMAR Table<br><br>- Write ACPI DMAR Table if VT-d is enabled.<br>- The entries are defined to follow FSP settings.<br><br>Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>---<br>M src/soc/intel/denverton_ns/acpi.c<br>M src/soc/intel/denverton_ns/include/soc/acpi.h<br>M src/soc/intel/denverton_ns/include/soc/iomap.h<br>M src/soc/intel/denverton_ns/include/soc/pci_devs.h<br>M src/soc/intel/denverton_ns/include/soc/systemagent.h<br>M src/soc/intel/denverton_ns/systemagent.c<br>6 files changed, 82 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25446/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c</span><br><span>index 9b99f11..853a6ee 100644</span><br><span>--- a/src/soc/intel/denverton_ns/acpi.c</span><br><span>+++ b/src/soc/intel/denverton_ns/acpi.c</span><br><span>@@ -32,6 +32,7 @@</span><br><span> #include <soc/soc_util.h></span><br><span> #include <soc/pmc.h></span><br><span> #include <soc/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span> </span><br><span> #define MWAIT_RES(state, sub_state) \</span><br><span> { \</span><br><span>@@ -335,3 +336,59 @@</span><br><span> }</span><br><span> </span><br><span> __attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static unsigned long acpi_fill_dmar(unsigned long current)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t vtbar;</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long tmp = current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ vtbar = read32((void *)(DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) &</span><br><span style="color: hsl(120, 100%, 40%);">+ MCH_VTBAR_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "DEFVTBAR:0x%x\n", vtbar);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!vtbar)</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_drhd(current,</span><br><span style="color: hsl(120, 100%, 40%);">+ DRHD_INCLUDE_PCI_ALL, 0, vtbar);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_drhd_ds_ioapic(current,</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_drhd_ds_msi_hpet(current,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_dmar_drhd_fixup(tmp, current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Create RMRR; see "VTD PLATFORM CONFIGURATION" in fsp log */</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = current;</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_rmrr(current, 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ RMRR_USB_BASE_ADDRESS,</span><br><span style="color: hsl(120, 100%, 40%);">+ RMRR_USB_LIMIT_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* reusing drdh functions for rmrr.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Should be Device Scope?</span><br><span style="color: hsl(120, 100%, 40%);">+ * IE remove _drhd */</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_drhd_ds_pci(current,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, XHCI_DEV, XHCI_FUNC);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_dmar_rmrr_fixup(tmp, current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long systemagent_write_acpi_tables(struct device *const dev,</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long current,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct acpi_rsdp *const rsdp)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Create DMAR table only if we have VT-d capability. */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 capid0_a = pci_read_config32(dev, CAPID0_A);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (capid0_a & VTD_DISABLE)</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_dmar_t *const dmar = (acpi_dmar_t *)current;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "ACPI: * DMAR\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += dmar->header.length;</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_align_current(current);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_add_table(rsdp, dmar);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h</span><br><span>index 588994d..f11a1a2 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/acpi.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/acpi.h</span><br><span>@@ -30,5 +30,8 @@</span><br><span> struct acpi_rsdp *rsdp);</span><br><span> void southcluster_inject_dsdt(device_t device);</span><br><span> void motherboard_fill_fadt(acpi_fadt_t *fadt);</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long systemagent_write_acpi_tables(struct device *const dev,</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long start,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct acpi_rsdp *const rsdp);</span><br><span> </span><br><span> #endif /* _DENVERTON_NS_ACPI_H_ */</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h</span><br><span>index a7548d4..8b25547 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/iomap.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/iomap.h</span><br><span>@@ -38,4 +38,8 @@</span><br><span> #define DEFAULT_HPET_ADDR CONFIG_HPET_ADDRESS</span><br><span> #define DEFAULT_SPI_BASE 0xfed01000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* "VTD PLATFORM CONFIGURATION" (Set to match FSP settings) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RMRR_USB_BASE_ADDRESS 0x3e2e0000</span><br><span style="color: hsl(120, 100%, 40%);">+#define RMRR_USB_LIMIT_ADDRESS 0x3e2fffff</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif /* _DENVERTON_NS_IOMAP_H_ */</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h</span><br><span>index b10a905..134586d 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h</span><br><span>@@ -202,4 +202,12 @@</span><br><span> #define PCH_DEV_LPC _PCH_DEV(LPC, 0)</span><br><span> #define PCH_DEV_SPI _PCH_DEV(LPC, 5)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* VT-d support value to match FSP settings */</span><br><span style="color: hsl(120, 100%, 40%);">+/* "PCH IOAPIC Config" */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_IOAPIC_PCI_BUS 0xF0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_IOAPIC_PCI_SLOT 31</span><br><span style="color: hsl(120, 100%, 40%);">+/* "PCH HPET Config" */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_HPET_PCI_BUS 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_HPET_PCI_SLOT 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif /* _DENVERTON_NS_PCI_DEVS_H_ */</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/systemagent.h b/src/soc/intel/denverton_ns/include/soc/systemagent.h</span><br><span>index a02aea3..4189d64 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/systemagent.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/systemagent.h</span><br><span>@@ -47,6 +47,9 @@</span><br><span> #define TOLUD 0xbc /* Top of Low Used Memory */</span><br><span> #define MASK_TOLUD 0xFFF00000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define CAPID0_A 0xe4</span><br><span style="color: hsl(120, 100%, 40%);">+#define VTD_DISABLE (1 << 23)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* SideBand B-UNIT */</span><br><span> #define B_UNIT 3</span><br><span> </span><br><span>@@ -73,6 +76,9 @@</span><br><span> #define MCH_BMISC_RESDRAM \</span><br><span> 0x01 /* Bit 0: 1 - reads targeting E-segment are routed to DRAM. */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MCH_VTBAR_OFFSET 0x6c80</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCH_VTBAR_MASK 0xfffff000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define MCH_BAR_BIOS_RESET_CPL 0x7078</span><br><span> #define RST_CPL_BIT (1 << 0)</span><br><span> #define PCODE_INIT_DONE (1 << 8)</span><br><span>diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c</span><br><span>index 0fcac3b..6d40ac9 100644</span><br><span>--- a/src/soc/intel/denverton_ns/systemagent.c</span><br><span>+++ b/src/soc/intel/denverton_ns/systemagent.c</span><br><span>@@ -34,6 +34,7 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/ramstage.h></span><br><span> #include <soc/systemagent.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/acpi.h></span><br><span> </span><br><span> #define _1ms 1</span><br><span> #define WAITING_STEP 100</span><br><span>@@ -341,6 +342,9 @@</span><br><span> .enable_resources = &pci_dev_enable_resources,</span><br><span> .init = &systemagent_init,</span><br><span> .ops_pci = &soc_pci_ops,</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span style="color: hsl(120, 100%, 40%);">+ .write_acpi_tables = systemagent_write_acpi_tables,</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> };</span><br><span> </span><br><span> /* IDs for System Agent device of Intel Denverton SoC */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25446">change 25446</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25446"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 </div>
<div style="display:none"> Gerrit-Change-Number: 25446 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>