<p>Julien Viard de Galbert has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25431">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/denverton_ns: Enable Fast Strings<br><br>Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>---<br>M src/soc/intel/denverton_ns/cpu.c<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>2 files changed, 7 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/25431/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c</span><br><span>index 528d2e5..fba6627 100644</span><br><span>--- a/src/soc/intel/denverton_ns/cpu.c</span><br><span>+++ b/src/soc/intel/denverton_ns/cpu.c</span><br><span>@@ -2,6 +2,7 @@</span><br><span>  * This file is part of the coreboot project.</span><br><span>  *</span><br><span>  * Copyright (C) 2015 - 2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Online SAS</span><br><span>  *</span><br><span>  * This program is free software; you can redistribute it and/or modify</span><br><span>  * it under the terms of the GNU General Public License as published by</span><br><span>@@ -39,6 +40,11 @@</span><br><span> </span><br><span>   printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n");</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   /* Enable Fast Strings */</span><br><span style="color: hsl(120, 100%, 40%);">+     msr = rdmsr(IA32_MISC_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+        msr.lo |= FAST_STRINGS_ENABLE_BIT;</span><br><span style="color: hsl(120, 100%, 40%);">+    wrmsr(IA32_MISC_ENABLE, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>      /* Enable Turbo */</span><br><span>   enable_turbo();</span><br><span> </span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index 4d1ac70..d56cc65 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -106,6 +106,7 @@</span><br><span> #define PRMRR_SUPPORTED (1 << 12)</span><br><span> </span><br><span> /* IA32_MISC_ENABLE bits */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FAST_STRINGS_ENABLE_BIT (1 << 0)</span><br><span> #define SPEED_STEP_ENABLE_BIT (1 << 16)</span><br><span> </span><br><span> /* Read BCLK from MSR */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25431">change 25431</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25431"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1 </div>
<div style="display:none"> Gerrit-Change-Number: 25431 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>