<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25455">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Use defined value for SPI flash MTRR<br><br>Replace an absolute value with a #define value in bootblock.  This is<br>in preparation for using an additional MTRR in a subsequent patch.<br><br>Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/include/soc/cpu.h<br>2 files changed, 13 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/25455/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>index fafaf07..db5c9b6 100644</span><br><span>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>@@ -25,6 +25,7 @@</span><br><span> #include <amdblocks/agesawrapper.h></span><br><span> #include <amdblocks/agesawrapper_call.h></span><br><span> #include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/cpu.h></span><br><span> #include <soc/northbridge.h></span><br><span> #include <soc/southbridge.h></span><br><span> #include <amdblocks/psp.h></span><br><span>@@ -61,7 +62,7 @@</span><br><span>    * todo: AGESA currently writes variable MTRRs.  Once that is</span><br><span>         *       corrected, un-hardcode this MTRR.</span><br><span>    */</span><br><span style="color: hsl(0, 100%, 40%);">-     mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH;</span><br><span>    set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h</span><br><span>index d2c412f..bf8ed49 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/cpu.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/cpu.h</span><br><span>@@ -16,6 +16,17 @@</span><br><span> #ifndef __STONEYRIDGE_CPU_H__</span><br><span> #define __STONEYRIDGE_CPU_H__</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ *  Set a variable MTRR in bootblock and/or romstage.  AGESA will use the lowest</span><br><span style="color: hsl(120, 100%, 40%);">+ *  numbered registers.  Any values defined below are subtracted from the</span><br><span style="color: hsl(120, 100%, 40%);">+ *  highest numbered registers.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ *  todo: Revisit this once AGESA no longer programs MTRRs.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_EARLY_VMTRR_FLASH 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void stoney_init_cpus(struct device *dev);</span><br><span> </span><br><span> #endif /* __STONEYRIDGE_CPU_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25455">change 25455</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25455"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3 </div>
<div style="display:none"> Gerrit-Change-Number: 25455 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>