<p>Patrick Rudolph would like Patrick Rudolph to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/25384">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">superio/nuvoton: Add support for NPCD378<br><br>The NPCD378 can be found on at least:<br>* HP Compaq 8200<br>* HP Compaq 8300<br><br>The datasheet is not publicly available, as HP has implement lots of<br>custom hardware. Add basic support for it, based on HP Compaq 8200.<br>The first eight LDN seem to be standard nuvoton compatible.<br><br>WARNING:<br>The remaining LDNs have been guessed and might be wrong !<br><br>The serial has been tested and is working.<br><br>Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/superio/nuvoton/Makefile.inc<br>A src/superio/nuvoton/npcd378/Kconfig<br>A src/superio/nuvoton/npcd378/Makefile.inc<br>A src/superio/nuvoton/npcd378/acpi/superio.asl<br>A src/superio/nuvoton/npcd378/npcd378.h<br>A src/superio/nuvoton/npcd378/superio.c<br>6 files changed, 324 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/25384/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc</span><br><span>index b557af2..0a4b357 100644</span><br><span>--- a/src/superio/nuvoton/Makefile.inc</span><br><span>+++ b/src/superio/nuvoton/Makefile.inc</span><br><span>@@ -25,3 +25,4 @@</span><br><span> subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776</span><br><span> subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d</span><br><span> subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += npcd378</span><br><span>diff --git a/src/superio/nuvoton/npcd378/Kconfig b/src/superio/nuvoton/npcd378/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..d405e29</span><br><span>--- /dev/null</span><br><span>+++ b/src/superio/nuvoton/npcd378/Kconfig</span><br><span>@@ -0,0 +1,18 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SUPERIO_NUVOTON_NPCD378</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_NUVOTON_COMMON_ROMSTAGE</span><br><span>diff --git a/src/superio/nuvoton/npcd378/Makefile.inc b/src/superio/nuvoton/npcd378/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..ca0c824</span><br><span>--- /dev/null</span><br><span>+++ b/src/superio/nuvoton/npcd378/Makefile.inc</span><br><span>@@ -0,0 +1,17 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+## (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += superio.c</span><br><span>diff --git a/src/superio/nuvoton/npcd378/acpi/superio.asl b/src/superio/nuvoton/npcd378/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..963704e</span><br><span>--- /dev/null</span><br><span>+++ b/src/superio/nuvoton/npcd378/acpi/superio.asl</span><br><span>@@ -0,0 +1,168 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013, 2016 secunet Security Networks AG</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Include this file into a mainboard's DSDT _SB device tree and it will</span><br><span style="color: hsl(120, 100%, 40%);">+ * expose the NPCD378 SuperIO and some of its functionality.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * It allows the change of IO ports, IRQs and DMA settings on logical</span><br><span style="color: hsl(120, 100%, 40%);">+ * devices, disabling and reenabling logical devices.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * LDN State</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x2 SP1 Implemented, untested</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x5 KBCK Implemented, untested</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef SUPERIO_CHIP_NAME</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_CHIP_NAME NPCD378</span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/acpi/pnp.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef PNP_DEFAULT_PSC</span><br><span style="color: hsl(120, 100%, 40%);">+#define PNP_DEFAULT_PSC Return (0) /* no power management */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Device(SUPERIO_DEV) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, EisaId("PNP0A05"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_STR, Unicode("Nuvoton NPCD378 Super I/O"))</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_UID, SUPERIO_UID(SUPERIO_DEV,))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SuperIO configuration ports */</span><br><span style="color: hsl(120, 100%, 40%);">+ OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ Field (CREG, ByteAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_ADDR_REG, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_DATA_REG, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x07),</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_LOGICAL_DEVICE, 8, /* Logical device selector */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x30),</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_DEVICE_ACTIVE, 1, /* Logical device activation */</span><br><span style="color: hsl(120, 100%, 40%);">+ ACT1, 1, /* Logical device activation */</span><br><span style="color: hsl(120, 100%, 40%);">+ ACT2, 1, /* Logical device activation */</span><br><span style="color: hsl(120, 100%, 40%);">+ ACT3, 1, /* Logical device activation */</span><br><span style="color: hsl(120, 100%, 40%);">+ ACT4, 1, /* Logical device activation */</span><br><span style="color: hsl(120, 100%, 40%);">+ ACT5, 1, /* Logical device activation */</span><br><span style="color: hsl(120, 100%, 40%);">+ ACT6, 1, /* Logical device activation */</span><br><span style="color: hsl(120, 100%, 40%);">+ ACT7, 1, /* Logical device activation */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x60),</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x62),</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x64),</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x70),</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_IRQ0, 8, /* First IRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0x72),</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_IRQ1, 8, /* Second IRQ */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Method (_CRS)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Announce the used I/O ports to the OS */</span><br><span style="color: hsl(120, 100%, 40%);">+ Return (ResourceTemplate () {</span><br><span style="color: hsl(120, 100%, 40%);">+ IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ })</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef PNP_ENTER_MAGIC_1ST</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef PNP_ENTER_MAGIC_2ND</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef PNP_ENTER_MAGIC_3RD</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef PNP_ENTER_MAGIC_4TH</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef PNP_EXIT_MAGIC_1ST</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef PNP_EXIT_SPECIAL_REG</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef PNP_EXIT_SPECIAL_VAL</span><br><span style="color: hsl(120, 100%, 40%);">+ #define PNP_ENTER_MAGIC_1ST 0x87</span><br><span style="color: hsl(120, 100%, 40%);">+ #define PNP_ENTER_MAGIC_2ND 0x87</span><br><span style="color: hsl(120, 100%, 40%);">+ #define PNP_EXIT_MAGIC_1ST 0xaa</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <superio/acpi/pnp_config.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef SUPERIO_SHOW_LPT</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_HID</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_DDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_PM_REG</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_PM_VAL</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_PM_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IO0</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IO1</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IRQ0</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IRQ1</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_DMA</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef PNP_DEVICE_ACTIVE</span><br><span style="color: hsl(120, 100%, 40%);">+ #define PNP_DEVICE_ACTIVE ACT3</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_PNP_LDN 1</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_PNP_IO0 0x08, 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <superio/acpi/pnp_generic.asl></span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef SUPERIO_SHOW_SP1</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_UART_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_UART_DDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_UART_PM_REG</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_UART_PM_VAL</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_UART_PM_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_UART_LDN 2</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <superio/acpi/pnp_uart.asl></span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef SUPERIO_SHOW_SP2</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_UART_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_UART_DDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_UART_PM_REG</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_UART_PM_VAL</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_UART_PM_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_UART_LDN 3</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <superio/acpi/pnp_uart.asl></span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef SUPERIO_SHOW_KBC</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_KBC_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_KBC_PS2M</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_KBC_PS2LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_KBC_PS2LDN 5</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_KBC_LDN 6</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <superio/acpi/pnp_kbc.asl></span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef SUPERIO_SHOW_GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_HID</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_DDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_PM_REG</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_PM_VAL</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_PM_LDN</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IO0</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IO1</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IO2</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IRQ0</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_IRQ1</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef SUPERIO_PNP_DMA</span><br><span style="color: hsl(120, 100%, 40%);">+ #undef PNP_DEVICE_ACTIVE</span><br><span style="color: hsl(120, 100%, 40%);">+ #define PNP_DEVICE_ACTIVE ACT3</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_PNP_LDN 8</span><br><span style="color: hsl(120, 100%, 40%);">+ #define SUPERIO_PNP_IO0 0x08, 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <superio/acpi/pnp_generic.asl></span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/superio/nuvoton/npcd378/npcd378.h b/src/superio/nuvoton/npcd378/npcd378.h</span><br><span>new file mode 100644</span><br><span>index 0000000..f17404b</span><br><span>--- /dev/null</span><br><span>+++ b/src/superio/nuvoton/npcd378/npcd378.h</span><br><span>@@ -0,0 +1,36 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SUPERIO_NUVOTON_NPCD378_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_NUVOTON_NPCD378_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Logical Device Numbers (LDN). */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Default Nuvoton hardware: */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_FDC 0x00 /* Floppy */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_PP 0x01 /* Parallel port */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_SP1 0x02 /* Com1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_SP2 0x03 /* Com2 & IR */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_AUX 0x05 /* PS/2 mouse */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_KBC 0x06 /* PS/2 keyboard */</span><br><span style="color: hsl(120, 100%, 40%);">+/* The following is guessed based on observation and might be wrong: */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_WDT1 0x07</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_GPIO689_V 0x08 /* exposes registers at IOBASE */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_I2C 0x15 /* Provides 35Khz at IOBASE + 0x9 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_PWR 0x1c /* Power control */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NPCD378_GPIOA 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SUPERIO_NUVOTON_NPCD378_H */</span><br><span>diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..340c276</span><br><span>--- /dev/null</span><br><span>+++ b/src/superio/nuvoton/npcd378/superio.c</span><br><span>@@ -0,0 +1,84 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 Advanced Micro Devices, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Felix Held <felix-coreboot@felixheld.de></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pnp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <pc80/keyboard.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdlib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/conf_mode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "npcd378.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void npcd378_init(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev->enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (dev->path.pnp.device) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: Might potentially need code for HWM or FDC etc. */</span><br><span style="color: hsl(120, 100%, 40%);">+ case NPCD378_KBC:</span><br><span style="color: hsl(120, 100%, 40%);">+ pc_keyboard_init(PROBE_AUX_DEVICE);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct device_operations ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .read_resources = pnp_read_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .set_resources = pnp_set_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_resources = pnp_enable_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable = pnp_alt_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+ .init = npcd378_init,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ops_pnp_mode = &pnp_conf_mode_8787_aa,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct pnp_info pnp_dev_info[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_FDC, PNP_IO0|PNP_IRQ0|PNP_DRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_PP, PNP_IO0|PNP_IRQ0|PNP_DRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_SP1, PNP_IO0|PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_SP2, PNP_IO0|PNP_IRQ0, 0x0ff8, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_AUX, PNP_IRQ0|PNP_DRQ0|PNP_DRQ1, 0x0fff, 0x0fff, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_KBC, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_DRQ0|PNP_DRQ1,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0fff, 0x0fff, },</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_WDT1, PNP_IO0|PNP_DRQ0|PNP_DRQ1|PNP_MSC8|PNP_MSC9|</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE, 0x0ff8},</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_GPIO689_V, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_DRQ0|PNP_DRQ1, 0x0ff8},</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_GPIO_PP_OD, PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|PNP_MSC8|PNP_MSC9|PNP_MSCA|</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE|PNP_DRQ0|PNP_DRQ1},</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_I2C, PNP_IO0|PNP_IO1|PNP_IRQ0|PNP_DRQ0|PNP_MSC0|</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_MSC1|PNP_MSC2|PNP_MSC3|PNP_MSC4|PNP_MSC5|PNP_MSC6|PNP_MSC7|</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_MSC8|PNP_MSC9|PNP_MSCA|PNP_MSCB|PNP_MSCC|PNP_MSCD|PNP_MSCE,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0ff8, 0x0ff8},</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_PWR, PNP_IO0|PNP_DRQ0|PNP_DRQ1, 0x0ff8 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { &ops, NPCD378_GPIOA, PNP_IO0|PNP_MSC0|PNP_MSC1|PNP_MSC2|PNP_MSC3|</span><br><span style="color: hsl(120, 100%, 40%);">+ PNP_MSC4|PNP_DRQ0|PNP_DRQ1, 0x0ff8},</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dev(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations superio_nuvoton_npcd378_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ CHIP_NAME("NUVOTON NPCD378 Super I/O")</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = enable_dev,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25384">change 25384</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25384"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38 </div>
<div style="display:none"> Gerrit-Change-Number: 25384 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>