<p>Patrick Rudolph would like Patrick Rudolph to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/25385">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/hp: Add new port compaq_8200_elite_sff<br><br>Add new port based on autoport.<br><br>The board uses a NPCD378 SuperIO, that is full of custom hardware.<br>The 8MiB flash SOIC-8 can be accessed after cutting of a part of the<br>DIMM slot holder. The flash IC has no diode, powering a part of the<br>board while flashing externaly, including the Standby-LED.<br><br>The following have been tested and is working:<br>* Native raminit with up to four DIMMs<br>* Libgfxinit on DisplayPort<br>* USB<br>* EHCI debug<br>* Serial on RS232<br>* Ethernet<br>* PCIe on x4<br>* PCIe on x16<br>* SATA<br>* Booting GNU Linux 4.14 using SeaBIOS as payload<br>* Flashing internaly<br><br>Untested:<br>* PS/2<br>* PCI slot<br>* LPT port<br>* VBIOS<br>* S3 resume<br><br>Not working:<br>* PSU fan managment (runs at 100%)<br>* Half of SuperIO functionality is unknown<br><br>TODO:<br>* Add SMBIOS tables for IPMI<br>* Reverse remaining SuperIO registers<br><br>Change-Id: I4ee8da6349222fda8b6c30a7210ffdd65c183439<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>A src/mainboard/hp/compaq_8200_elite_sff/Kconfig<br>A src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name<br>A src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc<br>A src/mainboard/hp/compaq_8200_elite_sff/acpi/ec.asl<br>A src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl<br>A src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl<br>A src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c<br>A src/mainboard/hp/compaq_8200_elite_sff/board_info.txt<br>A src/mainboard/hp/compaq_8200_elite_sff/cmos.default<br>A src/mainboard/hp/compaq_8200_elite_sff/cmos.layout<br>A src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb<br>A src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl<br>A src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads<br>A src/mainboard/hp/compaq_8200_elite_sff/gpio.c<br>A src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c<br>A src/mainboard/hp/compaq_8200_elite_sff/mainboard.c<br>A src/mainboard/hp/compaq_8200_elite_sff/romstage.c<br>17 files changed, 963 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/25385/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..f8c46f3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig</span><br><span>@@ -0,0 +1,64 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_HEWLETT_PACKARD_HP_COMPAQ_8200_ELITE_SFF_PC</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_8192</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_SOCKET_RPGA989</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_INT15</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_SANDYBRIDGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SERIRQ_CONTINUOUS_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_BD82X6X</span><br><span style="color: hsl(120, 100%, 40%);">+ select USE_NATIVE_RAMINIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LPC_TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ select TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_NUVOTON_NPCD378</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LIBGFXINIT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HAVE_IFD_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HAVE_ME_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default hp/compaq_8200_elite_sff</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "HP Compaq 8200 Elite SFF PC"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VGA_BIOS_FILE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "pci8086,0102.rom"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VGA_BIOS_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "8086,0102"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x103c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRAM_RESET_GATE_GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 60</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config USBDEBUG_HCD_INDEX</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 2</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..8de7363</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_HEWLETT_PACKARD_HP_COMPAQ_8200_ELITE_SFF_PC</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Compaq 8200 Elite SFF"</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..5592bfb</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/Makefile.inc</span><br><span>@@ -0,0 +1,3 @@</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/ec.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..e69de29</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/ec.asl</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..b99b363</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl</span><br><span>@@ -0,0 +1,23 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ </span><br><span style="color: hsl(120, 100%, 40%);">+Method(_WAK,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(Package(){0,0})</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PTS,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..9ec2949</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl</span><br><span>@@ -0,0 +1,25 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef SUPERIO_DEV</span><br><span style="color: hsl(120, 100%, 40%);">+#undef SUPERIO_PNP_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_DEV SIO0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_PNP_BASE 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_SHOW_SP2</span><br><span style="color: hsl(120, 100%, 40%);">+#define SUPERIO_SHOW_KBC</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/npcd378/acpi/superio.asl></span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..084e7e5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c</span><br><span>@@ -0,0 +1,33 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S3 by default */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S5 by default */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tcrt = 100;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tpsv = 90;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/board_info.txt b/src/mainboard/hp/compaq_8200_elite_sff/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..505aedd</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: desktop</span><br><span style="color: hsl(120, 100%, 40%);">+ROM IC: MX25L6405</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOIC-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: no</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: yes</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2013</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..2c056e4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Spew</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+volume=0x3</span><br><span style="color: hsl(120, 100%, 40%);">+sata_mode=AHCI</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..3261cee</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout</span><br><span>@@ -0,0 +1,114 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#390 2 r 0 unused?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+400 8 h 0 volume</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#411 10 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+421 1 e 9 sata_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#422 10 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+432 3 e 11 gfx_uma_size</span><br><span style="color: hsl(120, 100%, 40%);">+#435 549 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# SandyBridge MRC Scrambler Seed values</span><br><span style="color: hsl(120, 100%, 40%);">+896 32 r 0 mrc_scrambler_seed</span><br><span style="color: hsl(120, 100%, 40%);">+928 32 r 0 mrc_scrambler_seed_s3</span><br><span style="color: hsl(120, 100%, 40%);">+960 16 r 0 mrc_scrambler_seed_chk</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+9 0 AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+9 1 IDE</span><br><span style="color: hsl(120, 100%, 40%);">+11 0 32M</span><br><span style="color: hsl(120, 100%, 40%);">+11 1 64M</span><br><span style="color: hsl(120, 100%, 40%);">+11 2 96M</span><br><span style="color: hsl(120, 100%, 40%);">+11 3 128M</span><br><span style="color: hsl(120, 100%, 40%);">+11 4 160M</span><br><span style="color: hsl(120, 100%, 40%);">+11 5 192M</span><br><span style="color: hsl(120, 100%, 40%);">+11 6 224M</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 415 984</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..a88d06f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb</span><br><span>@@ -0,0 +1,216 @@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/sandybridge</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.link_frequency_270_mhz" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.ndid" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.use_spread_spectrum_clock" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_cpu_backlight" = "0x00000000"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_b_hotplug" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_c_hotplug" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_d_hotplug" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_port_select" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_off_delay" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_on_delay" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_cycle_delay" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_down_delay" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_up_delay" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_pch_backlight" = "0x00000000"</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_rPGA989</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_206ax </span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_acpower" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_battery" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_acpower" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_battery" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_acpower" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_battery" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xacac off</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "0x0065"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "docking_supported" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00fc0601"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x00fc0801"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "p_cnt_throttling_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_port_coalesce" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_interface_speed_support" = "0x3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x13"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_lvscc" = "0x0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_uvscc" = "0x0"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 on # Management Engine KT</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on # Intel Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on # USB2 EHCI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on # High Definition Audio Audio controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on # PCIe Port #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off # PCIe Port #2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off # PCIe Port #3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off # PCIe Port #4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on # PCIe Port #5</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off # PCIe Port #6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 on # PCIe Port #7</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 on # PCIe Port #8</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on # USB2 EHCI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # LPC bridge PCI-LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/nuvoton/npcd378</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.0 off end # Floppy</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1 on # Parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+ # global</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x1a = 0xb0</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x1b = 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x1c = 0xa8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x22 = 0x3f</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x27 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x2a = 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x2d = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ # parallel port</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x378</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0x07</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.2 off # COM1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x2f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.3 on # COM2, IR</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.5 on # Mouse</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0xc</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x71 = 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x74 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.6 on # Keyboard</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x0060</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x0064</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x71 = 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.7 on # WDT ?</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x620</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.8 on # GPIO ?</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x800</span><br><span style="color: hsl(120, 100%, 40%);">+ # IOBASE[0h:7h] read as zero</span><br><span style="color: hsl(120, 100%, 40%);">+ # IOBASE[8h:fh] unused</span><br><span style="color: hsl(120, 100%, 40%);">+ # IOBASE[10h] 0x2 always set, 0x4 toggle</span><br><span style="color: hsl(120, 100%, 40%);">+ # IOBASE[11h] 0xe0 toggle</span><br><span style="color: hsl(120, 100%, 40%);">+ # IOBASE[12h:19h] read only</span><br><span style="color: hsl(120, 100%, 40%);">+ # IOBASE[1ah:1dh] maps f4 - f7 read only</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x75 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf0 = 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf1 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf2 = 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf3 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf4 = 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf5 = 0x67</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf6 = 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf7 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.f on # GPIO OD ?</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x75 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf1 = 0x97</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf2 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf5 = 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xfe = 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.15 on # BUS ?</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x0680</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x0690</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x75 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1c on # Power Control ?</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x640</span><br><span style="color: hsl(120, 100%, 40%);">+ # writing to IOBASE[5h]</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0x0: Power off</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0x9: Power off and bricked</span><br><span style="color: hsl(120, 100%, 40%);">+ # until CMOS battery removed</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x75 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 2e.1e on # GPIO ?</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x660</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x74 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0x75 = 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+ drq 0xf4 = 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+ # skip the following, as it</span><br><span style="color: hsl(120, 100%, 40%);">+ # looks like remapped registers</span><br><span style="color: hsl(120, 100%, 40%);">+ #drq 0xf5 = 0x06</span><br><span style="color: hsl(120, 100%, 40%);">+ #drq 0xf6 = 0x60</span><br><span style="color: hsl(120, 100%, 40%);">+ #drq 0xfe = 0x03</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 4e.0 on end # TPM module</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on # SATA Controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off # SATA Controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # Host bridge Host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 on # PCIe Bridge for discrete graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on # Internal graphics VGA controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x1495</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..555028c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl</span><br><span>@@ -0,0 +1,44 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, // DSDT revision: ACPI v3.0</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", // OEM id</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", // OEM table id</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20141018 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // Some generic macros</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/model_206ax/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ /* global NVS and variables. */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/pch.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads b/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads</span><br><span>new file mode 100644</span><br><span>index 0000000..1152b3e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+-- it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+-- the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+-- (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+-- This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+-- but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+-- GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+--</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+with HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA;</span><br><span style="color: hsl(120, 100%, 40%);">+use HW.GFX.GMA.Display_Probing;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+private package GMA.Mainboard is</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ports : constant Port_List :=</span><br><span style="color: hsl(120, 100%, 40%);">+ (DP2,</span><br><span style="color: hsl(120, 100%, 40%);">+ Analog,</span><br><span style="color: hsl(120, 100%, 40%);">+ others => Disabled);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+end GMA.Mainboard;</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/gpio.c b/src/mainboard/hp/compaq_8200_elite_sff/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8786e28</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/gpio.c</span><br><span>@@ -0,0 +1,209 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio30 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio40 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio58 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio59 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio62 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio63 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio74 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio75 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set3 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set3_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set3_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set3_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set3_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..4b90aab</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c</span><br><span>@@ -0,0 +1,76 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0662, /* Codec Vendor / Device ID: Realtek */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x103c1495, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000000b, /* Number of 4 dword sets */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x01: Subsystem ID. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x0, 0x103c1495),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x14. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x15. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x15, 0x99130120),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x16. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x18. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x18, 0x01813c30),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x19. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x19, 0x02a11c3f),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1a. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1b. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1b, 0x0221101f),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1c. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1d. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1d, 0x40028101),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1e. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x80862805, /* Codec Vendor / Device ID: Intel */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x80861495, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000004, /* Number of 4 dword sets */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x01: Subsystem ID. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x3, 0x80861495),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x05. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x3, 0x05, 0x58560010),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x06. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x07. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[0] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..7ad4aa6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c</span><br><span>@@ -0,0 +1,30 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/gma/int15.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_PANEL_FIT_DEFAULT,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..a2ba76c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c</span><br><span>@@ -0,0 +1,84 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/byteorder.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pnp_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/npcd378/npcd378.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/nuvoton/common/nuvoton.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "northbridge/intel/sandybridge/raminit_native.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "southbridge/intel/bd82x6x/pch.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable SuperIO, TPM, Keyboard, LPT, COMA</span><br><span style="color: hsl(120, 100%, 40%);">+ * (COMB can be equip on expansion header)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_LPC_DEV, LPC_EN,</span><br><span style="color: hsl(120, 100%, 40%);">+ CNF2_LPC_EN |CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN |</span><br><span style="color: hsl(120, 100%, 40%);">+ COMB_LPC_EN | COMA_LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* COMA: 3F8h, COMB: 2F8h */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_early_init(int s3resume)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_config_superio(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))</span><br><span style="color: hsl(120, 100%, 40%);">+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_get_spd(spd_raw_data *spd, bool id_only)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: Only tested 1 and 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[3], 0x50, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[2], 0x51, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[1], 0x52, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[0], 0x53, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25385">change 25385</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25385"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4ee8da6349222fda8b6c30a7210ffdd65c183439 </div>
<div style="display:none"> Gerrit-Change-Number: 25385 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>