<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25389">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/poppy: Add variant for Atlas<br><br>Add a new variant of Poppy for the Atlas board.<br><br>BUG=b:75454415<br>TEST=tested on a P0 board. System boots and is mostly<br>functional, though some peripherals are not ready so there<br>are no touchpad/touchscreen devices configured yet.<br><br>Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/mainboard/google/poppy/Kconfig<br>M src/mainboard/google/poppy/Kconfig.name<br>A src/mainboard/google/poppy/variants/atlas/Makefile.inc<br>A src/mainboard/google/poppy/variants/atlas/devicetree.cb<br>A src/mainboard/google/poppy/variants/atlas/gpio.c<br>A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl<br>A src/mainboard/google/poppy/variants/atlas/include/variant/ec.h<br>A src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h<br>A src/mainboard/google/poppy/variants/atlas/memory.c<br>A src/mainboard/google/poppy/variants/atlas/nhlt.c<br>10 files changed, 1,064 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/25389/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig</span><br><span>index 7d98d0e..64230d6 100644</span><br><span>--- a/src/mainboard/google/poppy/Kconfig</span><br><span>+++ b/src/mainboard/google/poppy/Kconfig</span><br><span>@@ -25,6 +25,7 @@</span><br><span> </span><br><span> config DEVICETREE</span><br><span> string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/atlas/devicetree.cb" if BOARD_GOOGLE_ATLAS</span><br><span> default "variants/nami/devicetree.cb" if BOARD_GOOGLE_NAMI</span><br><span> default "variants/nautilus/devicetree.cb" if BOARD_GOOGLE_NAUTILUS</span><br><span> default "variants/soraka/devicetree.cb" if BOARD_GOOGLE_SORAKA</span><br><span>@@ -45,6 +46,7 @@</span><br><span> config GBB_HWID</span><br><span> string</span><br><span> depends on CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ATLAS TEST 1412" if BOARD_GOOGLE_ATLAS</span><br><span> default "POPPY TEST 8294" if BOARD_GOOGLE_POPPY</span><br><span> default "NAMI TEST 1669" if BOARD_GOOGLE_NAMI</span><br><span> default "NAUTILUS TEST 3013" if BOARD_GOOGLE_NAUTILUS</span><br><span>@@ -57,6 +59,12 @@</span><br><span> select NHLT_MAX98927</span><br><span> select NHLT_RT5663</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config INCLUDE_NHLT_BLOBS_ATLAS</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Include blobs for atlas audio."</span><br><span style="color: hsl(120, 100%, 40%);">+ select NHLT_DA7219</span><br><span style="color: hsl(120, 100%, 40%);">+ select NHLT_DMIC_2CH</span><br><span style="color: hsl(120, 100%, 40%);">+ select NHLT_MAX98373</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config INCLUDE_NHLT_BLOBS_NAUTILUS</span><br><span> bool "Include blobs for nautilus audio."</span><br><span> select NHLT_DA7219</span><br><span>@@ -75,6 +83,7 @@</span><br><span> </span><br><span> config MAINBOARD_FAMILY</span><br><span> string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Google_Atlas" if BOARD_GOOGLE_ATLAS</span><br><span> default "Google_Poppy" if BOARD_GOOGLE_POPPY</span><br><span> default "Google_Nami" if BOARD_GOOGLE_NAMI</span><br><span> default "Google_Nautilus" if BOARD_GOOGLE_NAUTILUS</span><br><span>@@ -82,6 +91,7 @@</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Atlas" if BOARD_GOOGLE_ATLAS</span><br><span> default "Poppy" if BOARD_GOOGLE_POPPY</span><br><span> default "Nami" if BOARD_GOOGLE_NAMI</span><br><span> default "Nautilus" if BOARD_GOOGLE_NAUTILUS</span><br><span>@@ -97,6 +107,7 @@</span><br><span> </span><br><span> config VARIANT_DIR</span><br><span> string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "atlas" if BOARD_GOOGLE_ATLAS</span><br><span> default "poppy" if BOARD_GOOGLE_POPPY</span><br><span> default "nami" if BOARD_GOOGLE_NAMI</span><br><span> default "nautilus" if BOARD_GOOGLE_NAUTILUS</span><br><span>@@ -123,6 +134,16 @@</span><br><span> select SPI_TPM</span><br><span> select TPM2</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config VARIANT_SPECIFIC_OPTIONS_ATLAS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool n</span><br><span style="color: hsl(120, 100%, 40%);">+ select CHROMEOS_WIFI_SAR if CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_MAX98373</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_DA7219</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_PS2_KEYBOARD</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_SPI_ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select EXCLUDE_NATIVE_SD_INTERFACE</span><br><span style="color: hsl(120, 100%, 40%);">+ select VARIANT_HAS_SPI_TPM if !VBOOT_MOCK_SECDATA</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config VARIANT_SPECIFIC_OPTIONS_POPPY</span><br><span> def_bool n</span><br><span> select DRIVERS_I2C_MAX98927</span><br><span>diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name</span><br><span>index d8d685e..686dd1d 100644</span><br><span>--- a/src/mainboard/google/poppy/Kconfig.name</span><br><span>+++ b/src/mainboard/google/poppy/Kconfig.name</span><br><span>@@ -1,3 +1,8 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GOOGLE_ATLAS</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Atlas"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_GOOGLE_BASEBOARD_POPPY</span><br><span style="color: hsl(120, 100%, 40%);">+ select VARIANT_SPECIFIC_OPTIONS_ATLAS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config BOARD_GOOGLE_POPPY</span><br><span> bool "Poppy"</span><br><span> select BOARD_GOOGLE_BASEBOARD_POPPY</span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/Makefile.inc b/src/mainboard/google/poppy/variants/atlas/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..c54d178</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/Makefile.inc</span><br><span>@@ -0,0 +1,18 @@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES = empty # 0b0000</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD # 0b0010</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD # 0b0100</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0101</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NUD # 0b0110</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0111</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b1000</span><br><span style="color: hsl(120, 100%, 40%);">+SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b1000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += memory.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += nhlt.c</span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..3d31c40</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>@@ -0,0 +1,338 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/skylake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Deep Sx states</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s3_enable_ac" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s3_enable_dc" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_ac" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_dc" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "GPP_B"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "GPP_E"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00fc0801"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c0201"</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC memory map range is 0x900-0x9ff</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen3_dec" = "0x00fc0901"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable S0ix</span><br><span style="color: hsl(120, 100%, 40%);">+ register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ProbelessTrace" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableLan" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableSata" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataMode" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableAzalia" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DspEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "IoBufferOwnership" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableTraceHub" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SsicPortEnable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Cio2Enable" = "0" # FIXME: enable once MIPI is ready</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaImguEnable" = "0" # FIXME: enable once MIPI is ready</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcEnabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsSdCardEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "IshEnable" = "0" # FIXME: enable once ISH is ready</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PttSwitch" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "InternalGfx" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SkipExtGfxScan" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Device4Enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "HeciEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIrqConfigSirqEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS3MinAssert" = "2" # 50ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS4MinAssert" = "1" # 1s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpSusMinAssert" = "1" # 500ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpAMinAssert" = "3" # 2s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmTimerDisabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "VmxEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tdp_pl2_override" = "15"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "psys_pmax" = "45"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tcc_offset" = "10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pch_trip_temp" = "75"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # VR Settings Configuration for 4 Domains</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Domain/Setting | SA | IA | GTUS | GTS |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi1Threshold | 20A | 20A | 20A | 20A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi2Threshold | 2A | 2A | 2A | 2A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Threshold | 1A | 1A | 1A | 1A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Enable | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi4Enable | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonSlope | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonOffset | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| IccMax | 4A | 24A | 24A | 24A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(2),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(4),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 1490,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 1420,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_IA_CORE]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(2),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(24),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 500,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 486,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_UNSLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(2),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(24),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 570,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 420,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_SLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(2),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = VR_CFG_AMP(24),</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 457,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 430,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCIe Root port 1 with SRCCLKREQ1#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpAdvancedErrorReporting[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpLtrEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # USB 2.0</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Empty</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # USB 3.0</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Touchscreen</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c[0]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rise_time_ns = 98,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fall_time_ns = 38,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Trackpad</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c[2]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_config[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scl_lcnt = 186,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scl_hcnt = 93,</span><br><span style="color: hsl(120, 100%, 40%);">+ .sda_hold = 36,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Camera</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c[3]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .rise_time_ns = 98,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fall_time_ns = 38,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c[4]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_config[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scl_lcnt = 176,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scl_hcnt = 95,</span><br><span style="color: hsl(120, 100%, 40%);">+ .sda_hold = 36,</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GSPI0 for cr50 TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gspi[0]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_mhz = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoDevMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C2] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C3] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C4] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart0] = PchSerialIoSkipInit,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 on end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.2 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C #0 - Touchscreen</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 off end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 on end # I2C #2 - Trackpad</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 on end # I2C #3 - Camera</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 off end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/max98373</span><br><span style="color: hsl(120, 100%, 40%);">+ register "vmon_slot_no" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "imon_slot_no" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "uid" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""RIGHT SPEAKER AMP""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "name" = ""MAXR""</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 31 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/max98373</span><br><span style="color: hsl(120, 100%, 40%);">+ register "vmon_slot_no" = "6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "imon_slot_no" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "uid" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""LEFT SPEAKER AMP""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "name" = ""MAXL""</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 32 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/da7219</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "btn_cfg" = "50"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "mic_det_thr" = "500"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jack_ins_deb" = "20"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jack_det_rate" = ""32ms_64ms""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jack_rem_deb" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "a_d_btn_thr" = "0xa"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "d_b_btn_thr" = "0x16"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "b_c_btn_thr" = "0x21"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c_mic_btn_thr" = "0x3e"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "btn_avg" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "adc_1bit_rpt" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "micbias_lvl" = "2600"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "mic_amp_in_sel" = ""diff""</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 1a on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #4 - Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_DW0_00"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCI Express Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCI Express Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCI Express Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCI Express Port 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off end # PCI Express Port 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 off end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/spi/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "compat_string" = ""google,cr50""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device spi 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.4 on end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.5 off end # SDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.6 off end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/google/chromeec</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..58b709e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/gpio.c</span><br><span>@@ -0,0 +1,390 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Leave eSPI pins untouched from default settings */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A0 : RCIN# ==> NC(TP763) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A0),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A1 : ESPI_IO0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A2 : ESPI_IO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A3 : ESPI_IO2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A4 : ESPI_IO3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A5 : ESPI_CS# */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A6 : SERIRQ ==> NC(TP764) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A6),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A7 : PIRQA# ==> NC(TP703) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A8 : CLKRUN# ==> NC(TP758)) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A8),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A9 : ESPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A10 : CLKOUT_LPC1 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A10),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A11 : PME# ==> NC(TP726) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A11),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A12 : BM_BUSY# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A12),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A13 : SUSWARN# ==> SUSWARN_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A14 : ESPI_RESET# */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A15 : SUSACK# ==> SUSACK_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A16 : SD_1P8_SEL ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A16),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A17 : SD_PWR_EN# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A17),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A18 : ISH_GP0 ==> ISH_GP0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A18),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A19 : ISH_GP1 ==> TRACKPAD_INT_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A20 : ISH_GP2 ==> ISH_UART0_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A20),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A21 : ISH_GP3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A21),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A22 : ISH_GP4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A22),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* A23 : ISH_GP5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B0 : CORE_VID0 ==> NC(TP42) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B0),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B1 : CORE_VID1 ==> NC(TP43) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B2 : VRALERT# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B2),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B3 : CPU_GP2 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B3),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B4 : CPU_GP3 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B4),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B5 : SRCCLKREQ0# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B5),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B7 : SRCCLKREQ2# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B8, 0, RSMRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B9 : SRCCLKREQ4# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B9),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B10 : SRCCLKREQ5# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B10),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B11 : EXT_PWR_GATE# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B11),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B12 : SLP_S0# ==> SLP_S0_L_G */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B13 : PLTRST# ==> PLT_RST_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B14 : SPKR ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B14),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B19 : GSPI1_CS# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B19),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B20 : GSPI1_CLK ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B20),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B21 : GSPI1_MISO ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B21),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B22 : GSPI1_MOSI ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B22),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B23 : SM1ALERT# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_B23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C0 : SMBCLK ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C0),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C1 : SMBDATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C2 : SMBALERT# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C2),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C3 : SML0CLK ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C3),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C4 : SML0DATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C4),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C5 : SML0ALERT# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C5),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C6 : SM1CLK ==> EC_IN_RW_OD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C7 : SM1DATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C8 : UART0_RXD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C8),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C9 : UART0_TXD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C9),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C10 : UART0_RTS# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C10),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C11 : UART0_CTS# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C11),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C18 : I2C1_SDA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C18),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C19 : I2C1_SCL ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_C19),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C22, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C23 : UART2_CTS# ==> PCH_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D0 : SPI1_CS# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D0),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D1 : SPI1_CLK ==> TRACKPAD_RESET_1V8_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D1, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D2 : SPI1_MISO ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D2),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D3 : SPI1_MOSI ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D3),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D4 : FASHTRIG ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D4),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D5 : ISH_I2C0_SDA ==> ISH_I2C0_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D6 : ISH_I2C0_SCL ==> ISH_I2C0_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D7 : ISH_I2C1_SDA ==> SPKR_IRQ_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D8 : ISH_I2C1_SCL ==> EN_CAMERA_PWR */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D8, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D9 : ISH_SPI_CS# ==> ISH_SPI_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_D9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D10 : ISH_SPI_CLK ==> ISH_SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_D10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D11 : ISH_SPI_MISO ==> ISH_SPI_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_D11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D12 : ISH_SPI_MOSI ==> ISH_SPI_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_D12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D13 : ISH_UART0_RXD ==> ISH_UART0_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_D13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D14 : ISH_UART0_TXD ==> ISH_UART0_TXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_D14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D15 : ISH_UART0_RTS# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D15),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D16 : ISH_UART0_CTS# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D16),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D17 : DMIC_CLK1 ==> PCH_CAMERA_RESET */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D17, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D18 : DMIC_DATA1 ==> PCH_CAMERA_CLOCK_ENABLE */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_D18, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D21 : SPI1_IO2 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D21),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D22 : SPI1_IO3 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_D22),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D23 : I2S_MCLK ==> I2S_MCLK_R */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E1 : SATAXPCIE1 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E2 : SATAXPCIE2 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E2),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E3 : CPU_GP0 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E3),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E4 : SATA_DEVSLP0 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E4),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E5 : SATA_DEVSLP1 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E5),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E6 : SATA_DEVSLP2 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E6),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E8 : SATALED# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E8),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_E11, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E12 : USB2_OC3# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E12),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E14 : DDPC_HPD1 ==> USB_C0_DP_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E15 : DDPD_HPD2 ==> EN_PP3300_DX_WLAN */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_E15, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E16 : DDPE_HPD3 ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E16),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E17 : EDP_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E18 : DDPB_CTRLCLK ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E18),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E19 : DDPB_CTRLDATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E19),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E20 : DDPC_CTRLCLK ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E20),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E21 : DDPC_CTRLDATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E21),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E22 : DDPD_CTRLCLK ==> TRACKPAD_SHDN_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_E22, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E23 : DDPD_CTRLDATA ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_E23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F0 : I2S2_SCLK ==> BOOT_BEEP_BCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F1 : I2S2_SFRM ==> BOOT_BEEP_BUFFER_OE */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_F1, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F2 : I2S2_TXD ==> BOOT_BEEP_LRCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F3 : I2S2_RXD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_F3),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F4 : I2C2_SDA ==> PCH_I2C2_TRACKPAD_1V8_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F5 : I2C2_SCL ==> PCH_I2C2_TRACKPAD_1V8_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F6 : I2C3_SDA ==> PCH_I2C3_CAMERA_1V8_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F7 : I2C3_SCL ==> PCH_I2C3_CAMERA_1V8_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F8 : I2C4_SDA ==> PCH_I2C4_AUDIO_1V8_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F9 : I2C4_SCL ==> PCH_I2C4_AUDIO_1V8_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F10 : I2C5_SDA ==> HP_IRQ_GPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F11 : I2C5_SCL ==> SPKR_RST_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_F11, 1, RSMRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F12 : EMMC_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F13 : EMMC_DATA0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F14 : EMMC_DATA1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F15 : EMMC_DATA2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F16 : EMMC_DATA3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F17 : EMMC_DATA4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F18 : EMMC_DATA5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F19 : EMMC_DATA6 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F20 : EMMC_DATA7 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F21 : EMMC_RCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F22 : EMMC_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* F23 : RSVD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_F23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G0 : SD_CMD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G1 : SD_DATA0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G2 : SD_DATA1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G3 : SD_DATA2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G4 : SD_DATA3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G5 : SD_CD# */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G6 : SD_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* G7 : SD_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD0: BATLOW# ==> PCH_BATLOW_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD4: SLP_S3# ==> SLP_S3_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD5: SLP_S4# ==> SLP_S4_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD6: SLP_A# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD6),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD7: RSVD ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD7),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD8: SUSCLK ==> PCH_SUSCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD9: SLP_WLAN# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD9),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD10: SLP_S5# ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD10),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD11: LANPHYC ==> NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPD11),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early pad configuration in bootblock */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B8, 0, RSMRST),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure UART pins are in native mode for H1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* C23 : UART2_CTS# ==> PCH_WP */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..bb42351</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl</span><br><span>@@ -0,0 +1,93 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_PASSIVE 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_CPU_CRITICAL 105</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_ID 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_SENSOR_NAME "systherm0"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_PASSIVE 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR0_CRITICAL 90</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_ID 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_SENSOR_NAME "systherm1"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_PASSIVE 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR1_CRITICAL 90</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_SENSOR_ID 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_SENSOR_NAME "systherm2"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_PASSIVE 65</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR2_CRITICAL 75</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_SENSOR_ID 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_SENSOR_NAME "systherm3"</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_PASSIVE 65</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_TSR3_CRITICAL 75</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef DPTF_ENABLE_FAN_CONTROL</span><br><span style="color: hsl(120, 100%, 40%);">+#define DPTF_ENABLE_CHARGER</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Charger performance states, board-specific values from charger and EC */</span><br><span style="color: hsl(120, 100%, 40%);">+Name (CHPS, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 255, 0xbb8, "mA", 0 }, /* 3000mA (MAX) */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 }, /* 2000mA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (DTRT, Package () {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on TSR0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on TSR1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on TSR2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CPU Throttle Effect on TSR3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Charger Throttle Effect on TSR0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Name (MPPC, Package ()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x2, /* Revision */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 3000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 7000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 5000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 5000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 200 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { /* Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 15000, /* PowerLimitMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 15000, /* PowerLimitMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000, /* TimeWindowMinimum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000, /* TimeWindowMaximum */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1000 /* StepSize */</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+})</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Include DPTF */</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/skylake/acpi/dptf/dptf.asl></span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h</span><br><span>new file mode 100644</span><br><span>index 0000000..22bcef5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h</span><br><span>@@ -0,0 +1,81 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __MAINBOARD_EC_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __MAINBOARD_EC_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/google/chromeec/ec_commands.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_SCI_EVENTS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_SMI_EVENTS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC can wake from S5 with lid or power button */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_S5_WAKE_EVENTS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * EC can wake from S3 with lid or power button or key press or</span><br><span style="color: hsl(120, 100%, 40%);">+ * mode change event.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_S3_WAKE_EVENTS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (MAINBOARD_EC_S5_WAKE_EVENTS |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Log EC wake events plus EC shutdown events */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MAINBOARD_EC_LOG_EVENTS \</span><br><span style="color: hsl(120, 100%, 40%);">+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\</span><br><span style="color: hsl(120, 100%, 40%);">+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * ACPI related definitions for ASL code.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable EC backed ALS device in ACPI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_ALS_DEVICE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable EC backed PD MCU device in ACPI */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_PD_MCU_DEVICE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable LID switch and provide wake pin for EC */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_LID_SWITCH</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __MAINBOARD_EC_H__ */</span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h b/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..f28fb31</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef EN_PP3300_DX_CAM</span><br><span style="color: hsl(120, 100%, 40%);">+#define EN_PP3300_DX_CAM GPP_D8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#undef EN_CAM_PMIC_RST_L</span><br><span style="color: hsl(120, 100%, 40%);">+#define EN_CAM_PMIC_RST_L GPP_D17</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __MAINBOARD_GPIO_H__ */</span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/memory.c b/src/mainboard/google/poppy/variants/atlas/memory.c</span><br><span>new file mode 100644</span><br><span>index 0000000..0b34e72</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/memory.c</span><br><span>@@ -0,0 +1,49 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* DQ byte map */</span><br><span style="color: hsl(120, 100%, 40%);">+static const u8 dq_map[][12] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 }</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* DQS CPU<>DRAM map */</span><br><span style="color: hsl(120, 100%, 40%);">+static const u8 dqs_map[][8] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 1, 3, 2, 4, 5, 6, 7 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 3, 2, 6, 7, 0, 1, 4, 5 },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Rcomp resistor */</span><br><span style="color: hsl(120, 100%, 40%);">+static const u16 rcomp_resistor[] = { 200, 81, 162 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Rcomp target */</span><br><span style="color: hsl(120, 100%, 40%);">+static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void variant_memory_params(struct memory_params *p)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ p->type = MEMORY_LPDDR3;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->dq_map = dq_map;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->dq_map_size = sizeof(dq_map);</span><br><span style="color: hsl(120, 100%, 40%);">+ p->dqs_map = dqs_map;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->dqs_map_size = sizeof(dqs_map);</span><br><span style="color: hsl(120, 100%, 40%);">+ p->rcomp_resistor = rcomp_resistor;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->rcomp_resistor_size = sizeof(rcomp_resistor);</span><br><span style="color: hsl(120, 100%, 40%);">+ p->rcomp_target = rcomp_target;</span><br><span style="color: hsl(120, 100%, 40%);">+ p->rcomp_target_size = sizeof(rcomp_target);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/nhlt.c b/src/mainboard/google/poppy/variants/atlas/nhlt.c</span><br><span>new file mode 100644</span><br><span>index 0000000..df62112</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/nhlt.c</span><br><span>@@ -0,0 +1,42 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <nhlt.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/nhlt.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void variant_nhlt_init(struct nhlt *nhlt)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 2 Channel DMIC array. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (nhlt_soc_add_dmic_array(nhlt, 2))</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Dialog DA7219 Headset codec. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Couldn't add Dialog DA7219 codec.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MAXIM Smart Amps for left and right speakers. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP0))</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Couldn't add Maxim 98373 codec.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t *oem_revision)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *oem_id = "GOOGLE";</span><br><span style="color: hsl(120, 100%, 40%);">+ *oem_table_id = "ATLASMAX";</span><br><span style="color: hsl(120, 100%, 40%);">+ *oem_revision = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25389">change 25389</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25389"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 </div>
<div style="display:none"> Gerrit-Change-Number: 25389 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>