<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25370">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cavium: Implement L2C functions without the need of BDK<br><br>* Implement functions to handle L2C.<br>* Don't use BDK functions any more.<br>* Flush L2 cache after loading the payload using memmove. Fixes payload booting.<br>TODO: Find out why L2 is not point of unification.<br><br>Change-Id: I697de35522af55fa8f40f4502e8245d31d07ba5f<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/soc/cavium/cn81xx/Makefile.inc<br>A src/soc/cavium/cn81xx/include/soc/l2c.h<br>A src/soc/cavium/cn81xx/l2c.c<br>M src/soc/cavium/cn81xx/sdram.c<br>4 files changed, 426 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/25370/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>index ac4dee2..d4fc57d 100644</span><br><span>--- a/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>+++ b/src/soc/cavium/cn81xx/Makefile.inc</span><br><span>@@ -38,7 +38,7 @@</span><br><span> romstage-y += spi.c</span><br><span> romstage-y += uart.c</span><br><span> romstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += l2c.c</span><br><span> romstage-y += sdram.c</span><br><span> romstage-y += ../common/cbmem.c</span><br><span> romstage-y += ../common/lame_string.c</span><br><span>@@ -87,6 +87,7 @@</span><br><span> ramstage-y += uart.c</span><br><span> ramstage-$(CONFIG_DRIVERS_UART) += uart.c</span><br><span> ramstage-y += sdram.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += l2c.c</span><br><span> </span><br><span> ramstage-y += bl31_plat_params.c</span><br><span> #BL31_MAKEARGS += PLAT=qemu M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)"</span><br><span>diff --git a/src/soc/cavium/cn81xx/include/soc/l2c.h b/src/soc/cavium/cn81xx/include/soc/l2c.h</span><br><span>new file mode 100644</span><br><span>index 0000000..f6e216e</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/cavium/cn81xx/include/soc/l2c.h</span><br><span>@@ -0,0 +1,83 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights</span><br><span style="color: hsl(120, 100%, 40%);">+ * reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * SPDX-License-Identifier: BSD-3-Clause</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __SOC_CAVIUM_CN81XX_L2C_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SOC_CAVIUM_CN81XX_L2C_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <inttypes.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct cn81xx_l2c_tad {</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 prf;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd0[0xf8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 pfc;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd1[0xfef8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 tag;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 stat;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd2[0xfff0];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 dll;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd3[0xfff8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 int_w1c;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 int_w1s;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd4[0x10];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 int_ena_w1c;</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 int_ena_w1s;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd5[0xffd0];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 timetwo;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd6[0xf8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 timeout;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd7[0xfef8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 err;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd8[0xf8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 tqd_err;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd9[0xf8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 ttg_err;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd10[0xfdf8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 tbf_bist_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd11[0xf8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 tdt_bist_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd12[0xf8];</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 ttg_bist_status;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+check_member(cn81xx_l2c_tad, ttg_bist_status, 0x70200 - 0x10000);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_L2DSBE (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_L2DDBE (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_SBFSBE (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_SBFDBE (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_FPFSBE (1 << 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_FPFDBE (1 << 5)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_TAGSBE (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_TAGDBE (1 << 9)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_NOWAY (1 << 10)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_WRNXM (1 << 13)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_RDNXM (1 << 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_RDDISLMC (1 << 15)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_WRDISLMC (1 << 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_LFBTO (1 << 17)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_GSYNCTO (1 << 18)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_TDDISOCI (1 << 34)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2C_TAD_INT_W1C_WRDISOCI (1 << 35)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Flush L2 Cache */</span><br><span style="color: hsl(120, 100%, 40%);">+void l2c_flush(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Unlock L2 Cache sets */</span><br><span style="color: hsl(120, 100%, 40%);">+size_t l2c_unlock_mem_region(uint64_t start, uint64_t len);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return the L2 Cache size in bytes */</span><br><span style="color: hsl(120, 100%, 40%);">+size_t l2c_get_cache_size_bytes(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return the number of sets in the L2 Cache */</span><br><span style="color: hsl(120, 100%, 40%);">+size_t l2c_get_num_sets(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return the number of associations in the L2 Cache */</span><br><span style="color: hsl(120, 100%, 40%);">+size_t l2c_get_num_assoc(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __SOC_CAVIUM_CN81XX_L2C_H__ */</span><br><span>diff --git a/src/soc/cavium/cn81xx/l2c.c b/src/soc/cavium/cn81xx/l2c.c</span><br><span>new file mode 100644</span><br><span>index 0000000..75c106d</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/cavium/cn81xx/l2c.c</span><br><span>@@ -0,0 +1,337 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights</span><br><span style="color: hsl(120, 100%, 40%);">+ * reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018-present Facebook, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * SPDX-License-Identifier: BSD-3-Clause</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <inttypes.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/asm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/l2c.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <program_loading.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <libbdk-arch/bdk-asm.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Flush L2 Cache */</span><br><span style="color: hsl(120, 100%, 40%);">+void l2c_flush(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The number of ways can be reduced with fuses, but the equations below</span><br><span style="color: hsl(120, 100%, 40%);">+ assume the max number of ways */</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t MAX_WAYS = 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t num_sets = l2c_get_num_sets();</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t num_ways = l2c_get_num_assoc();</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t cache_line_size = dcache_line_bytes();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "L2C: flush\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ int is_rtg = 1; /* Clear remote tags */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int l2_way = 0; l2_way < num_ways; l2_way++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int l2_set = 0; l2_set < num_sets; l2_set++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint64_t encoded = cache_line_size *</span><br><span style="color: hsl(120, 100%, 40%);">+ (l2_set + num_sets * (l2_way + (is_rtg * MAX_WAYS)));</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_CACHE_WBI_L2_INDEXED(encoded);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ is_rtg = 0; /* Clear local tags */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int l2_way = 0; l2_way < num_ways; l2_way++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (int l2_set = 0; l2_set < num_sets; l2_set++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint64_t encoded = cache_line_size *</span><br><span style="color: hsl(120, 100%, 40%);">+ (l2_set + num_sets * (l2_way + (is_rtg * MAX_WAYS)));</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_CACHE_WBI_L2_INDEXED(encoded);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void platform_segment_loaded(uintptr_t start, size_t size, int flags)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+#if ENV_RAMSTAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ l2c_flush();</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Unlock L2 Cache sets */</span><br><span style="color: hsl(120, 100%, 40%);">+size_t l2c_unlock_mem_region(uint64_t start, uint64_t len)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t cache_line_size = dcache_line_bytes();</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t cache_line_mask = cache_line_size - 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Round start/end to cache line boundaries */</span><br><span style="color: hsl(120, 100%, 40%);">+ len += start & cache_line_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ start &= ~cache_line_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ len = (len + cache_line_mask) & ~cache_line_mask;</span><br><span style="color: hsl(120, 100%, 40%);">+ void *ptr = (void *)start;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "L2C: unlock [%p, %p)\n", ptr, ptr + len);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ while (len > 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Must use invalidate version to release lock */</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_CACHE_WBI_L2(ptr);</span><br><span style="color: hsl(120, 100%, 40%);">+ ptr += cache_line_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ len -= cache_line_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return the L2 Cache size in bytes */</span><br><span style="color: hsl(120, 100%, 40%);">+size_t l2c_get_cache_size_bytes(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return l2c_get_num_sets() * l2c_get_num_assoc() *</span><br><span style="color: hsl(120, 100%, 40%);">+ dcache_line_bytes();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Register (SYSREG) ap_csselr_el1</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * AP Cache Size Selection Register</span><br><span style="color: hsl(120, 100%, 40%);">+ * Selects the current Cache Size ID Register, AP_CCSIDR_EL1, by specifying the</span><br><span style="color: hsl(120, 100%, 40%);">+ * required cache level and the cache type (either instruction or data cache).</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+union bdk_ap_csselr_el1</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t u;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct bdk_ap_csselr_el1_s</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ /**< [ 0: 0](R/W) Instruction not Data bit.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Data or unified cache.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Instruction cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ind : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ /**< [ 3: 1](R/W) Cache level of required cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t level : 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reserved_4_31 : 28;</span><br><span style="color: hsl(120, 100%, 40%);">+ } s;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Register (SYSREG) ap_ccsidr_el1</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * AP Current Cache Size ID Register</span><br><span style="color: hsl(120, 100%, 40%);">+ * This register provides information about the architecture of the currently</span><br><span style="color: hsl(120, 100%, 40%);">+ * selected cache. AP_CSSELR_EL1 selects which Cache Size ID Register is</span><br><span style="color: hsl(120, 100%, 40%);">+ * accessible.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+union bdk_ap_ccsidr_el1</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t u;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct bdk_ap_ccsidr_el1_cn81xx</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 2: 0](RO) Cache-line size, in</span><br><span style="color: hsl(120, 100%, 40%);">+ * (Log2(Number of bytes in cache line)) - 4.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CNXXXX, 128 bytes.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t linesize : 3;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 12: 3](RO) Associativity of cache minus 1, therefore a</span><br><span style="color: hsl(120, 100%, 40%);">+ * value of 0 indicates an associativity of 1. The associativity</span><br><span style="color: hsl(120, 100%, 40%);">+ * does not have to be a power of 2.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 31.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 38.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CN81XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 15.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CN80XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 7.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t associativity : 10;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 27: 13](RO) Number of sets in cache minus 1, therefore a</span><br><span style="color: hsl(120, 100%, 40%);">+ * value of 0 indicates 1 set in the cache. The number of sets</span><br><span style="color: hsl(120, 100%, 40%);">+ * does not have to be a power of 2.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CNXXXX L1D (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 0), is 7.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CNXXXX L1I (AP_CSSELR_EL1[LEVEL] = 0x0, AP_CSSELR_EL1[IND] = 1), is 15.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CN81XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 1023.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CN80XX L2 (AP_CSSELR_EL1[LEVEL] = 0x1, AP_CSSELR_EL1[IND] = 0), is 1023.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t numsets : 15;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 28: 28](RO) Indicates whether the selected cache level supports</span><br><span style="color: hsl(120, 100%, 40%);">+ * write-allocation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Write-allocation not supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Write-allocation supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CNXXXX does not apply as hardware managed coherence.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wa : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 29: 29](RO) Indicates whether the selected cache level supports</span><br><span style="color: hsl(120, 100%, 40%);">+ * read-allocation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Read-allocation not supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Read-allocation supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CNXXXX does not apply as hardware managed coherence.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t ra : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 30: 30](RO) Indicates whether the selected cache level supports</span><br><span style="color: hsl(120, 100%, 40%);">+ * write-back.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Write-back not supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Write-back supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CNXXXX does not apply as hardware managed coherence.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wb : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 31: 31](RO) Indicates whether the selected cache level supports</span><br><span style="color: hsl(120, 100%, 40%);">+ * write-through.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = Write-through not supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Write-through supported.</span><br><span style="color: hsl(120, 100%, 40%);">+ * For CNXXXX does not apply as hardware managed coherence.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t wt : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ } s;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return the number of sets in the L2 Cache */</span><br><span style="color: hsl(120, 100%, 40%);">+size_t l2c_get_num_sets(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Select the L2 cache */</span><br><span style="color: hsl(120, 100%, 40%);">+ union bdk_ap_csselr_el1 csselr_el1;</span><br><span style="color: hsl(120, 100%, 40%);">+ csselr_el1.u = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ csselr_el1.s.ind = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ csselr_el1.s.level = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_MSR(CSSELR_EL1, csselr_el1.u);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read its size */</span><br><span style="color: hsl(120, 100%, 40%);">+ union bdk_ap_ccsidr_el1 ccsidr_el1;</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_MRS(CCSIDR_EL1, ccsidr_el1.u);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "L2C: num sets %u\n", ccsidr_el1.s.numsets + 1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return ccsidr_el1.s.numsets + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// FIXME: Move to fuse.c</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIO_FUS_DAT3 0x87e003001418ll</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Register (RSL) mio_fus_dat3</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * MIO Fuse Data3 Register</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+union cavm_mio_fus_dat3</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t u;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cavm_mio_fus_dat3_cn81xx {</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 3: 0](RO) Coprocessor-clock PLL multiplier hardware limit. Indicates</span><br><span style="color: hsl(120, 100%, 40%);">+ * maximum value for PNR_MUL[5:1] straps. Any strap setting above this value</span><br><span style="color: hsl(120, 100%, 40%);">+ * will be ignored. A value of 0 indicates no hardware limit.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t pnr_pll_mul : 4;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 8: 4](RO) Core-clock PLL multiplier hardware limit. Indicates maximum</span><br><span style="color: hsl(120, 100%, 40%);">+ * value for PLL_MUL[5:1] straps. Any strap setting above this value will be</span><br><span style="color: hsl(120, 100%, 40%);">+ * ignored. A value of 0 indicates no hardware limit.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t core_pll_mul : 5;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 9: 9](RO) Reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Internal:</span><br><span style="color: hsl(120, 100%, 40%);">+ * When set to 1, TNS switching functionality is permanently disabled.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t tns_cripple : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 13: 10](RO) Fuse information - HNA information (cluster mask). */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t hna_info_clm : 4;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 16: 14](RO) Fuse information - HNA information (DTE). */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t hna_info_dte : 3;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 17: 17](RO) Fuse information - HNA disable (DTE). */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t nohna_dte : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 23: 18](RO) Fuse information - EMA1.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Internal:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Default value is 0x02. Soft or hard blow of these fuses will XOR with this</span><br><span style="color: hsl(120, 100%, 40%);">+ * value.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t ema1 : 6;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 24: 24](RO) Fuse information - HFA disable (HTE). */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t nodfa_dte : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 25: 25](RO) Fuse information - ZIP disable. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t nozip : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 26: 26](RO) Fuse information - efuse ignore. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t efus_ign : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 27: 27](RO) Fuse information - efuse lockdown. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t efus_lck : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 28: 28](RO) Fuse information - When 0, BAR2 size conforms to PCIe</span><br><span style="color: hsl(120, 100%, 40%);">+ * specification. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t bar2_sz_conf : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 30: 29](RO) Fuse information - ZIP information. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t zip_info : 2;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 31: 31](RO) If set, use the PLL output as the low-jitter reference clock</span><br><span style="color: hsl(120, 100%, 40%);">+ * to the rclk DLLs. Default is to use the internal input reference clock. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t use_int_refclk : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 34: 32](RO) Fuse information - L2C cripple:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0 = Full cache (16-way, 2 MB).</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x1 = 3/4 ways (12-way, 1.5 MB).</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x2 = 1/2 ways (8-way, 1 MB).</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x3 = 1/4 ways (4-way, 512 KB).</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x4-0x7 = Reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t l2c_crip : 3;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 35: 35](RO/H) Fuse information - coprocessor-clock PLL control. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t pll_half_dis : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 36: 36](RO) Fuse information - efuse lockdown. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t efus_lck_man : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 37: 37](RO) Fuse information - efuse lockdown. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t efus_lck_rsv : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 39: 38](RO) Select CLKF denominator for BWADJ value.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x0 = Selects CLKF/4.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x1 = Selects CLKF/2.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x2 = Selects CLKF/8.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t pll_bwadj_denom : 2;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 40: 40](RO) Fuse information - Select alternate PLL matrix. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t pll_alt_matrix : 1;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 44: 41](RO) Fuse information - HFA information (cluster mask). */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t dfa_info_clm : 4;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 47: 45](RO) Fuse information - HFA information (HTE). */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t dfa_info_dte : 3;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 57: 48](RO) Reserved. */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t pll_ctl : 10;</span><br><span style="color: hsl(120, 100%, 40%);">+/**< [ 63: 58](RO) Fuse information - EMA0.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Internal:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Default value is 0x11. Soft or hard blow of these fuses will XOR with this</span><br><span style="color: hsl(120, 100%, 40%);">+ * value.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t ema0 : 6;</span><br><span style="color: hsl(120, 100%, 40%);">+ } s;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Return the number of associations in the L2 Cache */</span><br><span style="color: hsl(120, 100%, 40%);">+size_t l2c_get_num_assoc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Select the L2 cache */</span><br><span style="color: hsl(120, 100%, 40%);">+ union bdk_ap_csselr_el1 csselr_el1;</span><br><span style="color: hsl(120, 100%, 40%);">+ csselr_el1.u = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ csselr_el1.s.ind = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ csselr_el1.s.level = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_MSR(CSSELR_EL1, csselr_el1.u);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Read its size */</span><br><span style="color: hsl(120, 100%, 40%);">+ union bdk_ap_ccsidr_el1 ccsidr_el1;</span><br><span style="color: hsl(120, 100%, 40%);">+ BDK_MRS(CCSIDR_EL1, ccsidr_el1.u);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Store it for use later */</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t ways = ccsidr_el1.s.associativity + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Early chips didn't update the number of ways based on fusing */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ways == 16) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The l2 can be reduced in 25% increments */</span><br><span style="color: hsl(120, 100%, 40%);">+ union cavm_mio_fus_dat3 mio_fus_dat3;</span><br><span style="color: hsl(120, 100%, 40%);">+ mio_fus_dat3.u = read64((u64 *)MIO_FUS_DAT3);</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (mio_fus_dat3.s.l2c_crip) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3: /* 1/4 size */</span><br><span style="color: hsl(120, 100%, 40%);">+ ways *= 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2: /* 1/2 size */</span><br><span style="color: hsl(120, 100%, 40%);">+ ways *= 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1: /* 3/4 size */</span><br><span style="color: hsl(120, 100%, 40%);">+ ways *= 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default: /* Full size */</span><br><span style="color: hsl(120, 100%, 40%);">+ ways *= 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ ways /= 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "L2C: num ways %zu\n", ways);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return ways;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c</span><br><span>index b6b42f7..420f1b0 100644</span><br><span>--- a/src/soc/cavium/cn81xx/sdram.c</span><br><span>+++ b/src/soc/cavium/cn81xx/sdram.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <console/console.h></span><br><span> #include <soc/sdram.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/l2c.h></span><br><span> #include <cbfs.h></span><br><span> </span><br><span> #include <soc/bdk/libbdk-arch/bdk-warn.h></span><br><span>@@ -89,13 +90,9 @@</span><br><span> }</span><br><span> </span><br><span> /* Unlock L2 now that DRAM works */</span><br><span style="color: hsl(0, 100%, 40%);">- if (node == bdk_numa_master())</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- uint64_t l2_size = bdk_l2c_get_cache_size_bytes(node);</span><br><span style="color: hsl(0, 100%, 40%);">- BDK_TRACE(INIT, "Unlocking L2\n");</span><br><span style="color: hsl(0, 100%, 40%);">- bdk_l2c_unlock_mem_region(node, 0, l2_size);</span><br><span style="color: hsl(0, 100%, 40%);">- bdk_watchdog_poke();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t l2_size = l2c_get_cache_size_bytes();</span><br><span style="color: hsl(120, 100%, 40%);">+ l2c_unlock_mem_region(0, l2_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ bdk_watchdog_poke();</span><br><span> </span><br><span> printk(BIOS_INFO, "SDRAM initialization finished.\n");</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25370">change 25370</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25370"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I697de35522af55fa8f40f4502e8245d31d07ba5f </div>
<div style="display:none"> Gerrit-Change-Number: 25370 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>