<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25375">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/octopus: Remove emmc tuning parameters from devicetree<br><br>Current emmc tuning parameters for octopus were copied over from other<br>boards and result in failure to boot from emmc. This change gets rid<br>of the emmc tuning parameters in devicetree. Once emmc tuning tests<br>are run for octopus, these parameters can be added back.<br><br>BUG=b:75986903<br>BRANCH=None<br>TEST=Verified that octopus boots from eMMC without any errors in<br>depthcharge.<br><br>Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f<br>Signed-off-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/mainboard/google/octopus/variants/baseboard/devicetree.cb<br>1 file changed, 0 insertions(+), 42 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/25375/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>index a19d247..7aa7038 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>@@ -24,48 +24,6 @@</span><br><span> # GPIO for PERST_0 (WLAN_PE_RST)</span><br><span> register "prt0_gpio" = "GPIO_164"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # EMMC TX DATA Delay 1</span><br><span style="color: hsl(0, 100%, 40%);">- # Refer to EDS-Vol2-16.33.</span><br><span style="color: hsl(0, 100%, 40%);">- # [14:8] steps of delay for HS400, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- # [6:0] steps of delay for SDR104/HS200, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- register "emmc_tx_data_cntl1" = "0x0C3A"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # EMMC TX DATA Delay 2</span><br><span style="color: hsl(0, 100%, 40%);">- # Refer to EDS-Vol2-16.34.</span><br><span style="color: hsl(0, 100%, 40%);">- # [30:24] steps of delay for SDR50, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- # [22:16] steps of delay for DDR50, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- # [14:8] steps of delay for SDR25/HS50, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- # [6:0] steps of delay for SDR12, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- register "emmc_tx_data_cntl2" = "0x28272929"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # EMMC RX CMD/DATA Delay 1</span><br><span style="color: hsl(0, 100%, 40%);">- # Refer to EDS-Vol2-16.35.</span><br><span style="color: hsl(0, 100%, 40%);">- # [30:24] steps of delay for SDR50, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- # [22:16] steps of delay for DDR50, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- # [14:8] steps of delay for SDR25/HS50, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- # [6:0] steps of delay for SDR12, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- register "emmc_rx_cmd_data_cntl1" = "0x003B263B"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # EMMC RX CMD/DATA Delay 2</span><br><span style="color: hsl(0, 100%, 40%);">- # Refer to EDS-Vol2-16.37.</span><br><span style="color: hsl(0, 100%, 40%);">- # [17:16] stands for Rx Clock before Output Buffer</span><br><span style="color: hsl(0, 100%, 40%);">- # [14:8] steps of delay for Auto Tuning Mode, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- # [6:0] steps of delay for HS200, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- register "emmc_rx_cmd_data_cntl2" = "0x10008"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # EMMC RX STROBE Delay</span><br><span style="color: hsl(0, 100%, 40%);">- # Refer to EDS-Vol2-16.36.</span><br><span style="color: hsl(0, 100%, 40%);">- # [16] Enable Auto Tuning for HS400 Strobe Path</span><br><span style="color: hsl(0, 100%, 40%);">- # [14:8] steps of delay for HS400 Mode 1, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- # [6:0] steps of delay for HS400 Mode 2, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- register "emmc_rx_strobe_cntl" = "0x0a0a"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- # EMMC TX COMMAND Delay</span><br><span style="color: hsl(0, 100%, 40%);">- # Refer to EDS-Vol2-16.32.</span><br><span style="color: hsl(0, 100%, 40%);">- # [14:8] steps of delay for DDR Mode, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- # [6:0] steps of delay for SDR Mode, each 125ps.</span><br><span style="color: hsl(0, 100%, 40%);">- register "emmc_tx_cmd_cntl" = "0x1305"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> # GPE configuration</span><br><span> # Note that GPE events called out in ASL code rely on this</span><br><span> # route, i.e., if this route changes then the affected GPE</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25375">change 25375</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f </div>
<div style="display:none"> Gerrit-Change-Number: 25375 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>