<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25364">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Limit xDCI feature when VBOOT is enabled<br><br>Use the common xDCI function to check if the controller is allowed<br>in the current mode before enabling it. Otherwise, disable the<br>PCI device if it has been enabled in devicetree.<br><br>Change-Id: I5aea15511c52d1191babf551feb237f4144683e4<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/soc/intel/apollolake/chip.c<br>M src/soc/intel/apollolake/xdci.c<br>2 files changed, 8 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/25364/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index cac2f11..1dd6daf 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -30,6 +30,7 @@</span><br><span> #include <intelblocks/fast_spi.h></span><br><span> #include <intelblocks/p2sb.h></span><br><span> #include <intelblocks/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/xdci.h></span><br><span> #include <fsp/api.h></span><br><span> #include <fsp/util.h></span><br><span> #include <intelblocks/cpulib.h></span><br><span>@@ -585,6 +586,12 @@</span><br><span> glk_fsp_silicon_init_params_cb(cfg, silconfig);</span><br><span> else</span><br><span> apl_fsp_silicon_init_params_cb(cfg, silconfig);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable xDCI controller if enabled in devicetree and allowed */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCH_DEVFN_XDCI);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!xdci_can_enable())</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->enabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ silconfig->UsbOtg = dev->enabled;</span><br><span> }</span><br><span> </span><br><span> struct chip_operations soc_intel_apollolake_ops = {</span><br><span>diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c</span><br><span>index 4c3047c..07207b3 100644</span><br><span>--- a/src/soc/intel/apollolake/xdci.c</span><br><span>+++ b/src/soc/intel/apollolake/xdci.c</span><br><span>@@ -54,7 +54,7 @@</span><br><span> * enabled. If it's disabled assume the switch was already done</span><br><span> * in FSP.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!dev->enabled || !xdci_dev->enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev->enabled || !xdci_dev->enabled || !xdci_can_enable())</span><br><span> return;</span><br><span> </span><br><span> printk(BIOS_INFO, "Putting port 0 into host mode.\n");</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25364">change 25364</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25364"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5aea15511c52d1191babf551feb237f4144683e4 </div>
<div style="display:none"> Gerrit-Change-Number: 25364 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>