<p>Duncan Laurie has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25366">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Limit xDCI feature when VBOOT is enabled<br><br>Use the common xDCI function to check if the controller is allowed<br>in the current mode before enabling it. Otherwise, disable the<br>PCI device if it has been enabled in devicetree.<br><br>To make the SOC behavior consistent the XdciEnable config option<br>is removed in favor of direct control by devicetree.cb.<br><br>Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1<br>Signed-off-by: Duncan Laurie <dlaurie@chromium.org><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/cannonlake/chip.h<br>3 files changed, 8 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/25366/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index dab6622..fc73210 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -70,6 +70,7 @@</span><br><span> select SOC_INTEL_COMMON_BLOCK_SPI</span><br><span> select SOC_INTEL_COMMON_BLOCK_TIMER</span><br><span> select SOC_INTEL_COMMON_BLOCK_UART</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_XDCI</span><br><span> select SOC_INTEL_COMMON_NHLT</span><br><span> select SOC_INTEL_COMMON_RESET</span><br><span> select SSE2</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index b2689b0..590bb45 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <fsp/api.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/xdci.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <soc/intel/common/vbt.h></span><br><span> #include <soc/pci_devs.h></span><br><span>@@ -180,7 +181,7 @@</span><br><span> {</span><br><span> int i;</span><br><span> FSP_S_CONFIG *params = &supd->FspsConfig;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct device *dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = SA_DEV_ROOT;</span><br><span> config_t *config = dev->chip_info;</span><br><span> </span><br><span> /* Parse device tree and enable/disable devices */</span><br><span>@@ -262,7 +263,11 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- params->XdciEnable = config->XdciEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable xDCI controller if enabled in devicetree and allowed */</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = dev_find_slot(0, PCH_DEVFN_USBOTG);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!xdci_can_enable())</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->enabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->XdciEnable = dev->enabled;</span><br><span> </span><br><span> /* PCI Express */</span><br><span> for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h</span><br><span>index 90956c3..2362c42 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.h</span><br><span>+++ b/src/soc/intel/cannonlake/chip.h</span><br><span>@@ -124,7 +124,6 @@</span><br><span> /* USB related */</span><br><span> struct usb2_port_config usb2_ports[16];</span><br><span> struct usb3_port_config usb3_ports[10];</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t XdciEnable;</span><br><span> uint8_t SsicPortEnable;</span><br><span> /* Wake Enable Bitmap for USB2 ports */</span><br><span> uint16_t usb2_wake_enable_bitmap;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25366">change 25366</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25366"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1 </div>
<div style="display:none"> Gerrit-Change-Number: 25366 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Duncan Laurie <dlaurie@chromium.org> </div>