<p>Sumeet R Pawnikar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25341">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/octopus/variants/baseboard: Set PL1 and PL2 value<br><br>This patch sets PL1 value to ~6W. Here, 8W setting gives<br>a run-time 6W actual measured power.<br>Also, this patch sets PL2 value to 15W.<br><br>BUG=None<br>BRANCH=None<br>TEST=Build and read the MSR 0x610.<br><br>Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6<br>Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com><br>---<br>M src/mainboard/google/octopus/variants/baseboard/devicetree.cb<br>1 file changed, 7 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/25341/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>index fb8fe54..5aafa6f 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>@@ -75,6 +75,13 @@</span><br><span>       register "gpe0_dw2" = "PMC_GPE_N_95_64"</span><br><span>  register "gpe0_dw3" = "PMC_GPE_NW_31_0"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+       # PL1 override 8000 mW: Due to error in the energy calculation for</span><br><span style="color: hsl(120, 100%, 40%);">+    # current VR solution. Experiments show that SoC TDP max (6W) can</span><br><span style="color: hsl(120, 100%, 40%);">+     # be reached when RAPL PL1 is set to 8W.</span><br><span style="color: hsl(120, 100%, 40%);">+      register "tdp_pl1_override_mw" = "8000"</span><br><span style="color: hsl(120, 100%, 40%);">+   # Set RAPL PL2 to 15W.</span><br><span style="color: hsl(120, 100%, 40%);">+        register "tdp_pl2_override_mw" = "15000"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>       # Minimum SLP S3 assertion width 28ms.</span><br><span>       register "slp_s3_assertion_width_usecs" = "28000"</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25341">change 25341</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25341"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6 </div>
<div style="display:none"> Gerrit-Change-Number: 25341 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> </div>