<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25344">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">ACPI: Add SPCR table<br><br>The SPCR ACPI table is used to indicate whether a serial port or a<br>non-legacy UART interface is available for use with Microsoft<br>Windows Emergency Management Services (EMS).<br><br>It is also used by Linux and BITS to determine the serial port<br>configuration.<br><br>For more information, see the Reference Serial Port Console<br>Redirection Table - SPCR_Tbl-v102-CP.docx<br><br>BUG=b:74392237<br>TEST=After following commit, Build Grunt, verify SPCR table<br><br>Change-Id: I2ff31da061c88a6f3e3cf76285f8ab78ee35509c<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/arch/x86/include/arch/acpi.h<br>M src/superio/Makefile.inc<br>A src/superio/acpi/Makefile.inc<br>A src/superio/acpi/spcr.c<br>4 files changed, 239 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/25344/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h</span><br><span>index 5418420..3be5c9e 100644</span><br><span>--- a/src/arch/x86/include/arch/acpi.h</span><br><span>+++ b/src/arch/x86/include/arch/acpi.h</span><br><span>@@ -4,6 +4,7 @@</span><br><span> * Copyright (C) 2004 SUSE LINUX AG</span><br><span> * Copyright (C) 2004 Nick Barker</span><br><span> * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.</span><br><span> * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,</span><br><span> * Raptor Engineering</span><br><span> * Copyright (C) 2016 Siemens AG</span><br><span>@@ -63,6 +64,7 @@</span><br><span> #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */</span><br><span> #define OEM_ID "CORE " /* Must be exactly 6 bytes long! */</span><br><span> #define ASLC "CORE" /* Must be exactly 4 bytes long! */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_SIG "SPCR" /* Must be exactly 4 bytes long! */</span><br><span> </span><br><span> /*</span><br><span> * The assigned ACPI ID for the coreboot project is 'BOOT'</span><br><span>@@ -636,6 +638,77 @@</span><br><span> u32 status;</span><br><span> } __packed acpi_tstate_t;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* SPCR (Serial Port Console Redirection) */</span><br><span style="color: hsl(120, 100%, 40%);">+typedef struct acpi_spcr {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct acpi_table_header header;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 interface_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct acpi_gen_regaddr base_address;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 interrupt_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 irq;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 global_system_interrupt;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 baud_rate;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 parity;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 stop_bits;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 flow_control;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 terminal_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reserved_4;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 pci_device_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 pci_vendor_id;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pci_bus_number;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pci_device_number;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pci_function_number;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 pci_flags;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pci_segment;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved_5;</span><br><span style="color: hsl(120, 100%, 40%);">+} __packed acpi_spcr_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_SPCR_REV 1 /* 1.0 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_16550_INTERFACE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_16450_INTERFACE 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_RESERVED_MUST_BE_ZERO 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_NO_INTERRUPT_SUPPORTED 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_PIC_INTERRUPT_SUPPORTED (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_APIC_INTERRUPT_SUPPORTED (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_SAPIC_INTERRUPT_SUPPORTED (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_NO_IRQ 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_NO_GSI 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_9600_BAUD 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_19200_BAUD 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_57600_BAUD 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_115200_BAUD 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_NO_PARITY 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_1_STOP_BIT 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_NO_FLOW_CONTROL 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_DCD_FLOW_CONTROL (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_RTS_CTS_FLOW_CONTROL (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_XON_XOFF_FLOW_CONTROL (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_TERM_VT100 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_TERM_VT100_PLUS 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_TERM_VT_UTF8 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_TERM_ANSI 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_DID_NOT_A_PCI_DEVICE 0xffff</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_VID_NOT_A_PCI_DEVICE 0xffff</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_BUS_NOT_A_PCI_DEVICE 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_DEV_NOT_A_PCI_DEVICE 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_FUNC_NOT_A_PCI_DEVICE 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_PCI_FLAG_NOT_A_PCI_DEVICE 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_PCI_FLAG_NONE 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_PCI_FLAG_DO_NOT_SUPRESS_PNP_ENUM (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPCR_PCI_SEGMENT_0 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> unsigned long fw_cfg_acpi_tables(unsigned long start);</span><br><span> </span><br><span> /* These are implemented by the target port or north/southbridge. */</span><br><span>@@ -732,6 +805,8 @@</span><br><span> void acpi_write_hest(acpi_hest_t *hest,</span><br><span> unsigned long (*acpi_fill_hest)(acpi_hest_t *hest));</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long acpi_create_spcr(unsigned long current);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,</span><br><span> acpi_hest_esd_t *esd, u16 type, void *data, u16 len);</span><br><span> </span><br><span>diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc</span><br><span>index 5fc0ecd..630aa77 100644</span><br><span>--- a/src/superio/Makefile.inc</span><br><span>+++ b/src/superio/Makefile.inc</span><br><span>@@ -13,6 +13,7 @@</span><br><span> ## GNU General Public License for more details.</span><br><span> ##</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += acpi</span><br><span> subdirs-y += fintek</span><br><span> subdirs-y += intel</span><br><span> subdirs-y += ite</span><br><span>diff --git a/src/superio/acpi/Makefile.inc b/src/superio/acpi/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..7c12d3c</span><br><span>--- /dev/null</span><br><span>+++ b/src/superio/acpi/Makefile.inc</span><br><span>@@ -0,0 +1,14 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += spcr.c</span><br><span>diff --git a/src/superio/acpi/spcr.c b/src/superio/acpi/spcr.c</span><br><span>new file mode 100644</span><br><span>index 0000000..b64d786</span><br><span>--- /dev/null</span><br><span>+++ b/src/superio/acpi/spcr.c</span><br><span>@@ -0,0 +1,149 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Google, LLC</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * ACPI - Create the Serial Port Console Redirection Table (SPCR)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/uart.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t get_spcr_baudrate(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (get_uart_baudrate()) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 115200:</span><br><span style="color: hsl(120, 100%, 40%);">+ return SPCR_115200_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 57600:</span><br><span style="color: hsl(120, 100%, 40%);">+ return SPCR_57600_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 119200:</span><br><span style="color: hsl(120, 100%, 40%);">+ return SPCR_19200_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 9600:</span><br><span style="color: hsl(120, 100%, 40%);">+ return SPCR_9600_BAUD;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_WARNING, "SPCR Error: Unsupported baud rate.\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ "SPCR table supports 115200, 57600, 19200, or 9600.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Serial Port Console Redirection Table (SPCR)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long acpi_create_spcr(unsigned long current)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_spcr_t *spcr = (void *)current;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!current)</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_header_t *header = &(spcr->header);</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t baud, acpi_space_type, address_width;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t irq = SPCR_NO_IRQ;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t interupt_type = SPCR_NO_INTERRUPT_SUPPORTED;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t address;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "ACPI: * SPCR\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ baud = get_spcr_baudrate();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (baud == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) || IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Memory Mapped serial port. */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_space_type=ACPI_ADDRESS_SPACE_MEMORY;</span><br><span style="color: hsl(120, 100%, 40%);">+ address = CONFIG_TTYS0_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))</span><br><span style="color: hsl(120, 100%, 40%);">+ address_width = 32;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ address_width = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IO Mapped 8250/16450/16550 UART configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_space_type=ACPI_ADDRESS_SPACE_IO;</span><br><span style="color: hsl(120, 100%, 40%);">+ address = CONFIG_TTYS0_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+ address_width = 8;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO - Add a better way than just assuming standard IRQs */</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((CONFIG_UART_FOR_CONSOLE == 0) ||</span><br><span style="color: hsl(120, 100%, 40%);">+ (CONFIG_UART_FOR_CONSOLE == 2)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ irq = 4;</span><br><span style="color: hsl(120, 100%, 40%);">+ interupt_type = SPCR_PIC_INTERRUPT_SUPPORTED;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else if ((CONFIG_UART_FOR_CONSOLE == 1) ||</span><br><span style="color: hsl(120, 100%, 40%);">+ (CONFIG_UART_FOR_CONSOLE == 3)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ irq = 3;</span><br><span style="color: hsl(120, 100%, 40%);">+ interupt_type = SPCR_PIC_INTERRUPT_SUPPORTED;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_WARNING, "SPCR Warning: IRQ is not known."</span><br><span style="color: hsl(120, 100%, 40%);">+ "Defaulting to NONE.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk( BIOS_ERR, "SPCR Error: unknown UART type\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Prepare the header */</span><br><span style="color: hsl(120, 100%, 40%);">+ memset((void *)spcr, 0, sizeof(acpi_spcr_t));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(header->signature, SPCR_SIG, 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ header->length = sizeof(acpi_spcr_t);</span><br><span style="color: hsl(120, 100%, 40%);">+ header->revision = ACPI_SPCR_REV;</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(header->oem_id, OEM_ID, 6);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(header->asl_compiler_id, ASLC, 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ header->asl_compiler_revision = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->interface_type = SPCR_16550_INTERFACE;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->reserved_1 = SPCR_RESERVED_MUST_BE_ZERO;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->reserved_2 = SPCR_RESERVED_MUST_BE_ZERO;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->reserved_3 = SPCR_RESERVED_MUST_BE_ZERO;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->base_address.space_id = acpi_space_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->base_address.bit_width = address_width;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->base_address.bit_offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->base_address.access_size = ACPI_ACCESS_SIZE_UNDEFINED;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->base_address.addrl = address;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->base_address.addrh = 0x0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->interrupt_type = interupt_type;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->irq = irq;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->global_system_interrupt = SPCR_NO_GSI;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->baud_rate = baud;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->parity = SPCR_NO_PARITY;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->stop_bits = SPCR_1_STOP_BIT;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->flow_control = SPCR_NO_FLOW_CONTROL;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->terminal_type = SPCR_TERM_VT100;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->reserved_4 = SPCR_RESERVED_MUST_BE_ZERO;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->pci_device_id = SPCR_DID_NOT_A_PCI_DEVICE;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->pci_vendor_id = SPCR_VID_NOT_A_PCI_DEVICE;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->pci_bus_number = SPCR_BUS_NOT_A_PCI_DEVICE;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->pci_device_number = SPCR_DEV_NOT_A_PCI_DEVICE;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->pci_function_number = SPCR_FUNC_NOT_A_PCI_DEVICE;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->pci_flags = SPCR_PCI_FLAG_NOT_A_PCI_DEVICE;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->pci_segment = SPCR_PCI_SEGMENT_0;</span><br><span style="color: hsl(120, 100%, 40%);">+ spcr->reserved_5 = SPCR_RESERVED_MUST_BE_ZERO;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ header->checksum = acpi_checksum((void *)spcr, spcr->header.length);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return current + sizeof(acpi_spcr_t);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25344">change 25344</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25344"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2ff31da061c88a6f3e3cf76285f8ab78ee35509c </div>
<div style="display:none"> Gerrit-Change-Number: 25344 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>