<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25325">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/broadwell: If L1 Sub state is disabled, do not set capability<br><br>I finally found out why disabling the L1 sub state option did not<br>prevent some NVMe drives from locking up in L1 substate. I expect<br>that the disabled L1 substate initialization that coreboot does<br>is negated because Linux might itself configure it if it finds the<br>capability enabled on the PCIe root port.<br><br>Removing the capability from the PCIe root port when L1 sub states<br>are disabled in the configuration should fix the problem.<br><br>This was not tested because it's a difficult issue to reproduce and<br>I do not have the problematic hardware that caused it anymore.<br><br>Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265<br>Signed-off-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net><br>---<br>M src/soc/intel/broadwell/pcie.c<br>1 file changed, 4 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25325/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c</span><br><span>index aff66a3..cf25749 100644</span><br><span>--- a/src/soc/intel/broadwell/pcie.c</span><br><span>+++ b/src/soc/intel/broadwell/pcie.c</span><br><span>@@ -558,7 +558,10 @@</span><br><span>                 (1 << 29) | 0x10001);</span><br><span> </span><br><span>      /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */</span><br><span style="color: hsl(0, 100%, 40%);">-      pci_update_config32(dev, 0x200, ~0xffff, 0x001e);</span><br><span style="color: hsl(120, 100%, 40%);">+     if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE))</span><br><span style="color: hsl(120, 100%, 40%);">+           pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);</span><br><span style="color: hsl(120, 100%, 40%);">+    else</span><br><span style="color: hsl(120, 100%, 40%);">+          pci_update_config32(dev, 0x200, ~0xfffff, 0);</span><br><span> </span><br><span>    pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6),</span><br><span>              (1 << 20) | (3 << 6));</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25325">change 25325</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25325"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265 </div>
<div style="display:none"> Gerrit-Change-Number: 25325 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>