<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25328">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O port<br><br>The LPC I/O ports for EC communication were not set properly,<br>causing ectool to fail to read the Index I/O from the EC.<br><br>The EC Index I/O is on port 0x380 and the LPC I/O port needs to be<br>decoded by the PCI device for it to be accessible.<br><br>Correct the value for the Librem 13v1, 13v2 and 15v3.<br><br>Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a<br>Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm><br>---<br>M src/mainboard/purism/librem13v1/devicetree.cb<br>M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb<br>M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb<br>3 files changed, 10 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/25328/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/purism/librem13v1/devicetree.cb b/src/mainboard/purism/librem13v1/devicetree.cb</span><br><span>index ba38070..c916e9a 100644</span><br><span>--- a/src/mainboard/purism/librem13v1/devicetree.cb</span><br><span>+++ b/src/mainboard/purism/librem13v1/devicetree.cb</span><br><span>@@ -18,6 +18,10 @@</span><br><span> register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms</span><br><span> register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges are in 0x380-0x383 & 0x80-0x8f</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00000381"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c0081"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # Port 0 is HDD</span><br><span> # Port 3 is M.2 NGFF</span><br><span> register "sata_port_map" = "0x9"</span><br><span>diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>index 1fc19a5..50e484b 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb</span><br><span>@@ -15,9 +15,9 @@</span><br><span> register "gpe0_dw1" = "GPP_D"</span><br><span> register "gpe0_dw2" = "GPP_E"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span style="color: hsl(0, 100%, 40%);">- register "gen1_dec" = "0x00fc0801"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gen2_dec" = "0x000c0201"</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges are in 0x380-0x383 & 0x80-0x8f</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00000381"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c0081"</span><br><span> </span><br><span> # Enable "Intel Speed Shift Technology"</span><br><span> register "speed_shift_enable" = "1"</span><br><span>diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>index 647f054..a52e4b7 100644</span><br><span>--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb</span><br><span>@@ -15,9 +15,9 @@</span><br><span> register "gpe0_dw1" = "GPP_D"</span><br><span> register "gpe0_dw2" = "GPP_E"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span style="color: hsl(0, 100%, 40%);">- register "gen1_dec" = "0x00fc0801"</span><br><span style="color: hsl(0, 100%, 40%);">- register "gen2_dec" = "0x000c0201"</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges are in 0x380-0x383 & 0x80-0x8f</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00000381"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c0081"</span><br><span> </span><br><span> # Enable "Intel Speed Shift Technology"</span><br><span> register "speed_shift_enable" = "1"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25328">change 25328</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a </div>
<div style="display:none"> Gerrit-Change-Number: 25328 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>