<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25287">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/kahlee: Update GPIOs based on board ID<br><br>BUG=b:73078053<br>TEST=build & boot Grunt<br><br>Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286<br>Signed-off-by: Martin Roth <martinroth@chromium.org><br>---<br>M src/mainboard/google/kahlee/bootblock/bootblock.c<br>M src/mainboard/google/kahlee/mainboard.c<br>M src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h<br>4 files changed, 75 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/25287/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>index 1eb18f1..a7207b0 100644</span><br><span>--- a/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <soc/southbridge.h></span><br><span> #include <variant/ec.h></span><br><span> #include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <boardid.h></span><br><span> </span><br><span> void bootblock_mainboard_early_init(void)</span><br><span> {</span><br><span>@@ -30,6 +31,16 @@</span><br><span> </span><br><span> gpios = variant_early_gpio_table(&num_gpios);</span><br><span> sb_program_gpios(gpios, num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: Remove when no longer needed */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program additional early GPIOs */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (board_id() < 2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpios = variant_early_gpio_table_old(&num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_program_gpios(gpios, num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpios = variant_early_gpio_table_new(&num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_program_gpios(gpios, num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span> void bootblock_mainboard_init(void)</span><br><span>diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c</span><br><span>index e82569e..2a1c3eb 100644</span><br><span>--- a/src/mainboard/google/kahlee/mainboard.c</span><br><span>+++ b/src/mainboard/google/kahlee/mainboard.c</span><br><span>@@ -30,6 +30,7 @@</span><br><span> #include <variant/ec.h></span><br><span> #include <variant/thermal.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <boardid.h></span><br><span> </span><br><span> /***********************************************************</span><br><span> * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.</span><br><span>@@ -168,6 +169,13 @@</span><br><span> gpios = variant_gpio_table(&num_gpios);</span><br><span> sb_program_gpios(gpios, num_gpios);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: Remove when no longer needed */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Reprogram additional GPIOs */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (board_id() < 2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gpios = variant_gpio_table_old(&num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_program_gpios(gpios, num_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> gpes = get_gpe_table(&num);</span><br><span> gpe_configure_sci(gpes, num);</span><br><span> </span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>index cab7611..2e0a07e 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>@@ -83,9 +83,6 @@</span><br><span> /* GPIO_26 - APU_PCIE_RST_L */</span><br><span> PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_40 - EMMC_BRIDGE_RST_L - Currently unused */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_40, PULL_UP),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* GPIO_42 - S5_MUX_CTRL */</span><br><span> PAD_NF(GPIO_42, S5_MUX_CTRL, PULL_NONE),</span><br><span> </span><br><span>@@ -110,9 +107,6 @@</span><br><span> /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */</span><br><span> PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_93 - EMMC_RST_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_93, HIGH),</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* GPIO_95 - SD_CLK */</span><br><span> /* GPIO_96 - SD_CMD */</span><br><span> /* GPIO_97 - SD_D0 */</span><br><span>@@ -195,6 +189,22 @@</span><br><span> PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset_new[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_40 - EMMC_BRIDGE_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_GPI(GPIO_40, PULL_DOWN),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_93 - EMMC_RST */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_GPO(GPIO_93, LOW),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset_old[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_40 - EMMC_BRIDGE_RST_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_GPI(GPIO_40, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_93 - EMMC_RST_L */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_GPO(GPIO_93, HIGH),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {</span><br><span> /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */</span><br><span> PAD_NF(GPIO_2, WAKE_L, PULL_UP),</span><br><span>@@ -202,8 +212,8 @@</span><br><span> /* GPIO_10 - SLP_S0_L (currently not used) */</span><br><span> PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO_12 - Unused (TP126) */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_12, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_12 - EN_PP3300_TRACKPAD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_GPO(GPIO_12, HIGH),</span><br><span> </span><br><span> /* GPIO_13 - APU_PEN_PDCT_ODL (currently not used) */</span><br><span> PAD_GPI(GPIO_13, PULL_UP),</span><br><span>@@ -233,7 +243,7 @@</span><br><span> PAD_GPO(GPIO_90, HIGH),</span><br><span> </span><br><span> /* GPIO_91 - EN_PP3300_TRACKPAD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPO(GPIO_91, HIGH),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_GPI(GPIO_91, PULL_UP),</span><br><span> </span><br><span> /* GPIO_102 - EN_SD_SOCKET_PWR */</span><br><span> PAD_NF(GPIO_102, SD0_PWR_CTRL, PULL_DOWN),</span><br><span>@@ -254,6 +264,15 @@</span><br><span> PAD_GPI(GPIO_135, PULL_UP),</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram_old[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_12 - Unused (TP126) */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_GPI(GPIO_12, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO_91 - EN_PP3300_TRACKPAD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_GPO(GPIO_91, HIGH),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> const __attribute__((weak))</span><br><span> struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size)</span><br><span> {</span><br><span>@@ -268,6 +287,28 @@</span><br><span> return gpio_set_stage_ram;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* TODO: Remove when no longer needed */</span><br><span style="color: hsl(120, 100%, 40%);">+const __attribute__((weak))</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_old(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = ARRAY_SIZE(gpio_set_stage_reset_old);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_set_stage_reset_old;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const __attribute__((weak))</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_new(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = ARRAY_SIZE(gpio_set_stage_reset_new);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_set_stage_reset_new;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const __attribute__((weak))</span><br><span style="color: hsl(120, 100%, 40%);">+struct soc_amd_stoneyridge_gpio *variant_gpio_table_old(size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = ARRAY_SIZE(gpio_set_stage_ram_old);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_set_stage_ram_old;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * GPE setup table must match ACPI GPE ASL</span><br><span> * { gevent, gpe, direction, level }</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>index e5a348a..9744113 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h</span><br><span>@@ -31,5 +31,11 @@</span><br><span> int variant_get_ehci_oc_map(uint16_t *usb_oc_map);</span><br><span> const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table(size_t *size);</span><br><span> const struct soc_amd_stoneyridge_gpio *variant_gpio_table(size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+/* TODO: Remove when no longer needed */</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_old( \</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *variant_early_gpio_table_new( \</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+const struct soc_amd_stoneyridge_gpio *variant_gpio_table_old(size_t *size);</span><br><span> </span><br><span> #endif /* __BASEBOARD_VARIANTS_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25287">change 25287</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286 </div>
<div style="display:none"> Gerrit-Change-Number: 25287 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>