<p>Zhongze Hu has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25258">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/fizz: Enable I2C bus 2<br><br>I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase<br>it was idle.<br><br>Google CFM add-in card is going to use this I2C bus so it needs to be<br>re-enabled.<br><br>BUG=b:73006317<br>TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is<br>working properly.<br><br>Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808<br>---<br>M src/mainboard/google/fizz/devicetree.cb<br>1 file changed, 4 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/25258/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb</span><br><span>index e7654cf..2b87e31 100644</span><br><span>--- a/src/mainboard/google/fizz/devicetree.cb</span><br><span>+++ b/src/mainboard/google/fizz/devicetree.cb</span><br><span>@@ -296,9 +296,9 @@</span><br><span> </span><br><span> # Must leave UART0 enabled or SD/eMMC will not work as PCI</span><br><span> register "SerialIoDevMode" = "{</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexI2C0] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C0] = PchSerialIoPci,</span><br><span> [PchSerialIoIndexI2C1] = PchSerialIoDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- [PchSerialIoIndexI2C2] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C2] = PchSerialIoPci,</span><br><span> [PchSerialIoIndexI2C3] = PchSerialIoDisabled,</span><br><span> [PchSerialIoIndexI2C4] = PchSerialIoDisabled,</span><br><span> [PchSerialIoIndexI2C5] = PchSerialIoPci,</span><br><span>@@ -329,9 +329,9 @@</span><br><span> device pci 14.0 on end # USB xHCI</span><br><span> device pci 14.1 off end # USB xDCI (OTG)</span><br><span> device pci 14.2 on end # Thermal Subsystem</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.0 off end # I2C #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C #0</span><br><span> device pci 15.1 off end # I2C #1</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 15.2 off end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 on end # I2C #2</span><br><span> device pci 15.3 off end # I2C #3</span><br><span> device pci 16.0 on end # Management Engine Interface 1</span><br><span> device pci 16.1 off end # Management Engine Interface 2</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25258">change 25258</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25258"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808 </div>
<div style="display:none"> Gerrit-Change-Number: 25258 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Zhongze Hu <frankhu@chromium.org> </div>