<p>Nick Vaccaro has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25256">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/zoombini: Enable NVMe<br><br>BUG=b:72120814<br>BRANCH=master<br>TEST=none<br><br>Change-Id: I64ab38dda78345c1f3d7d3f2bf3cb04c19290ceb<br>Signed-off-by: Nick Vaccaro <nvaccaro@google.com><br>---<br>M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>1 file changed, 6 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/25256/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>index 44ea0bb..512354e 100644</span><br><span>--- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb</span><br><span>@@ -51,6 +51,11 @@</span><br><span>   register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span>      register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   # Enable Root port 8 (PCIe port 9) for NVMe</span><br><span style="color: hsl(120, 100%, 40%);">+   register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+  register "PcieClkSrcUsage[3]" = "8"</span><br><span style="color: hsl(120, 100%, 40%);">+       register "PcieClkSrcClkReq[3]" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>   device domain 0 on</span><br><span>           device pci 00.0 on  end # Host Bridge</span><br><span>                device pci 02.0 on  end # Integrated Graphics Device</span><br><span>@@ -81,7 +86,7 @@</span><br><span>             device pci 1c.5 off end # PCI Express Port 6</span><br><span>                 device pci 1c.6 off end # PCI Express Port 7</span><br><span>                 device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(0, 100%, 40%);">-            device pci 1d.0 off end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+          device pci 1d.0 on  end # PCI Express Port 9</span><br><span>                 device pci 1d.1 off end # PCI Express Port 10</span><br><span>                device pci 1d.2 off end # PCI Express Port 11</span><br><span>                device pci 1d.3 off end # PCI Express Port 12</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25256">change 25256</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25256"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I64ab38dda78345c1f3d7d3f2bf3cb04c19290ceb </div>
<div style="display:none"> Gerrit-Change-Number: 25256 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com> </div>