<p>Kin Wai Ng would like Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela and Rizwan Qureshi to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/25241">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/coffeelake: Fix up GPIO pad mappings to Coffee Lake H RVP11<br><br>1.<br>Fixing GPIO pad mappings also resolves reboot issues in UEFI shell and Yocto.<br><br>2.<br>Fix up ACPI GPIO device for CFL-H<br><br>Change-Id: I3acf0a0e3101eadb3464baf8e1a7ba5b32804777<br>Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com><br>---<br>M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c<br>M src/soc/intel/coffeelake/acpi/gpio.asl<br>M src/soc/intel/coffeelake/gpio.c<br>M src/soc/intel/coffeelake/include/soc/gpio.h<br>M src/soc/intel/coffeelake/include/soc/gpio_defs.h<br>M src/soc/intel/coffeelake/include/soc/gpio_soc_defs.h<br>6 files changed, 547 insertions(+), 604 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/25241/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index 44632e9..f62a891</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c</span><br><span>@@ -19,276 +19,194 @@</span><br><span> </span><br><span> /* Pad configuration in ramstage*/</span><br><span> static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPPC */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A0 : RCINB_TIME_SYNC_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A1 : ESPI_IO_0 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A2 : ESPI_IO_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A3 : ESPI_IO_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A4 : ESPI_IO_3 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A5 : ESPI_CSB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A6 : SERIRQ */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A7 : PRIQAB_GSP10_CS1B */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A8 : CLKRUNB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_A8, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A9 : CLKOUT_LPC_0_ESPI_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A10 : CLKOUT_LPC_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A11 : PMEB_GSP11_CS1B */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_SCI_LOW(GPP_A11, UP_20K, DEEP, LEVEL),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A12 : BM_BUSYB_ISH__GP_6 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A13 : SUSWARNB_SUSPWRDNACK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_A13, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A14 : SUS_STATB_ESPI_RESETB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A15 : SUSACKB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_A15, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A16 : SD_1P8_SEL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_A16, 0, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* A18 : ISH_GP_0 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A19 : ISH_GP_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A20 : aduio codec irq */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A21 : ISH_GP_3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A22 : ISH_GP_4 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* A23 : ISH_GP_5 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* B0 : CORE_VID_0 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B1 : CORE_VID_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B2 : VRALERTB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B3 : CPU_GP_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B4 : CPU_GP_3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_B4, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B5 : SRCCLKREQB_0 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B6 : SRCCLKREQB_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B7 : SRCCLKREQB_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B8 : SRCCLKREQB_3 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B9 : SRCCLKREQB_4 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B10 : SRCCLKREQB_5 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B11 : EXT_PWR_GATEB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B12 : SLP_S0B */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B13 : PLTRSTB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B14 : SPKR */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_B14, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B15 : GSPI0_CS0B */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_B15, 0, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B16 : GSPI0_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B17 : GSPI0_MISO */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_B17, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B18 : GSPI0_MOSI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_B18, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* B19 : GSPI1_CS0B */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B20 : GSPI1_CLK_NFC_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B21 : GSPI1_MISO_NFC_CLKREQ */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B22 : GSP1_MOSI */</span><br><span style="color: hsl(0, 100%, 40%);">- /* B23 : SML1ALERTB_PCHHOTB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_B23, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+ // Gpio's for Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC_LOW(GPP_A11, UP_20K, PLTRST), // I2S_CODEC_INT</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_B11 // SSP_MCLK</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D17 // DMIC_CLK_1</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D18 // DMIC_DATA_1</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D19 // DMIC_CLK_0</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D20 // DMIC_DATA_0</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H10, 1, PLTRST), // Audio Power Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_J11, 1, PLTRST), // SPEAKER PD</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* C0 : SMBCLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C1 : SMBDATA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C2 : SMBALERTB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_C2, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C3 : SML0CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C4 : SML0DATA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C5 : SML0ALERTB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C6 : SML1CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C7 : SML1DATA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C8 : UART0_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C9 : UART0_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C10 : UART0_RTSB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_C10, 0, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C11 : UART0_CTSB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_SCI_LOW(GPP_C11, UP_20K, DEEP, LEVEL),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C12 : UART1_RXD_ISH_UART1_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_C12, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C13 : UART1_RXD_ISH_UART1_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C14 : UART1_RXD_ISH_UART1_RTSB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C15 : UART1_RXD_ISH_UART1_CTSB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_C15, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* C16 : I2C0_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C17 : I2C0_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C18 : I2C1_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C19 : I2C1_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C20 : UART2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C21 : UART2_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C22 : UART2_RTSB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* C23 : UART2_CTSB */</span><br><span style="color: hsl(120, 100%, 40%);">+ //Bios Recovery</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_INT(GPP_F10, NONE, PLTRST, LEVEL), // BIOS_RECOVERY</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* D0 : SPI1_CSB_BK_0 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D1 : SPI1_CLK_BK_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D2 : SPI1_MISO_IO_1_BK_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D3 : SPI1_MOSI_IO_0_BK_3 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D4 : IMGCLKOUT_0_BK_4 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D5 : ISH_I2C0_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D6 : ISH_I2C0_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D7 : ISH_I2C1_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D8 : ISH_I2C1_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D9 : ISH_SPI_CSB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_D9, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D10 : ISH_SPI_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST, EDGE_SINGLE, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D13 : ISH_UART0_RXD_SML0BDATA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_D13, 1, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D14 : ISH_UART0_TXD_SML0BCLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_D14, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */</span><br><span style="color: hsl(0, 100%, 40%);">- /* D16 : ISH_UART0_CTSB_SML0BALERTB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D17 : DMIC_CLK_1_SNDW3_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D18 : DMIC_DATA_1_SNDW3_DATA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D19 : DMIC_CLK_0_SNDW4_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D20 : DMIC_DATA_0_SNDW4_DATA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D21 : SPI1_IO_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D22 : SPI1_IO_3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* D23 : SPP_MCLK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E0 : SATAXPCIE_0_SATAGP_0 */</span><br><span style="color: hsl(0, 100%, 40%);">-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">- /* E1 : SATAXPCIE_1_SATAGP_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E2 : SATAXPCIE_2_SATAGP_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E3 : CPU_GP_0 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E4 : SATA_DEVSLP_0 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E5 : SATA_DEVSLP_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E6 : SATA_DEVSLP_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E7 : CPU_GP_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E8 : SATA_LEDB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E9 : USB2_OCB_0_GP_BSSB_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E10 : USB2_OCB_1_GP_BSSB_DI */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E11 : USB2_OCB_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E12 : USB2_OCB_3 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E13 : DDSP_HPD_0_DISP_MISC_0 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E14 : DDSP_HPD_0_DISP_MISC_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E15 : DDSP_HPD_0_DISP_MISC_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E16 : EMMC_EN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_E16, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* E17 : EDP_HPD_DISP_MISC_4 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E18 : DDPB_CTRLCLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E19 : DDPB_CTRLDATA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E20 : DDPC_CTRLCLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E21 : DDPC_CTRLDATA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E22 : DDPD_CTRLCLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* E23 : DDPD_CTRLDATA */</span><br><span style="color: hsl(120, 100%, 40%);">+ //CSME</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, LEVEL), // ME_PG_LED</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* F0 : CNV_GNSS_PA_BLANKING */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPP_F0, NONE, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F1 : CNV_GNSS_FAT */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F2 : CNV_GNSS_SYSCK */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F3 : GPP_F_3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F4 : CNV_BRI_DT_UART0_RTSB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F5 : CNV_BRI_RSP_UART0_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F6 : CNV_RGI_DT_UART0_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F7 : CNV_RGI_DT_RSP_UART9_CTSB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F8 : CNV_MFUART2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F9 : CNV_MFUART2_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F10 : GPP_F_10 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_F10, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* F11 : EMMC_CMD */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F12 : EMMC_DATA0 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F13 : EMMC_DATA1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F14 : EMMC_DATA2 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F15 : EMMC_DATA3 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F16 : EMMC_DATA4 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F17 : EMMC_DATA5 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F18 : EMMC_DATA6 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F19 : EMMC_DATA9 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F20 : EMMC_RCLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F21 : EMMC_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F22 : EMMC_RESETB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* F23 : BIOS_REC */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI(GPP_F23, UP_20K, DEEP),</span><br><span style="color: hsl(0, 100%, 40%);">- /* G0 : SD3_D2 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* G1 : SD3_D0_SD4_RCLK_P */</span><br><span style="color: hsl(0, 100%, 40%);">- /* G2 : SD3_D1_SD4_RCLK_N */</span><br><span style="color: hsl(0, 100%, 40%);">- /* G3 : SD3_D2 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* G4 : SD3_D3 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* G5 : SD3_CDB */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* G6 : SD3_CLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* G7 : SD3_WP */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ //Display</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_I0 // DDSP_HPD_0</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_I1 // DDSP_HPD_1</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_I2 // DDSP_HPD_2</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_I5 // DDI1_CTRL_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_I6 // DDI1_CTRL_DATA</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_I7 // DDI2_CTRL_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_I8 // DDI2_CTRL_DATA</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* H0 : SSP2_SCLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H1 : SSP2_SFRM */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H2 : SSP2_TXD */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H3 : SSP2_RXD */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H4 : I2C2_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H5 : I2C2_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H6 : I2C3_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H7 : I2C3_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H8 : I2C4_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H9 : I2C4_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H10 : I2C5_SDA_ISH_I2C2_SDA */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H10, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H11 : I2C5_SCL_ISH_I2C2_SCL */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H11, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H12, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H13, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H14 : M2_SKT2_CFG_2 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H14, 0, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H15 : M2_SKT2_CFG_3 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H15, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H16 : CAM5_PWR_EN */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H16, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H17 : CAM5_FLASH_STROBE */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H17, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H18 : BOOTMPC */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H19 : TIMESYNC_0 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H19, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H20 : IMGCLKOUT_1 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H21 : GPPC_H_21 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* H22 : GPPC_H_22 */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPO(GPP_H22, 1, PLTRST),</span><br><span style="color: hsl(0, 100%, 40%);">- /* H23 : GPPC_H_23 */</span><br><span style="color: hsl(120, 100%, 40%);">+ //EC</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B23, 1, PLTRST), // EC_SLP_S0_CS_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C6 // SML1_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C7 // SML1_DATA</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), // EC_SMI_N</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_K11, UP_20K, PLTRST, LEVEL), // RUNTIME_SCI</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD_0 : BATLOWB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD_1 : ACPRESENT */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD_2 : LAN_WAKEB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD_3 : PWRBTNB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD_4 : SLP_S3B */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD_5 : SLP_S4B */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD_6 : SLP_AB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD_7 : GPD_7 */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD-8 : SUSCLK */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD-9 : SLP_WLANB */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD-10 : SLP_5B */</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPD_11 : LANPHYPC */</span><br><span style="color: hsl(120, 100%, 40%);">+ //eDP</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F19 // L_VDDEN</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F20 // L_BKLTEN</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F21 // L_BKLTCTL</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_I4 // EDP_HPD</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ //FPS</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D9 // GSPI2_CS_FPS</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D10 // GSPI2_CLK_FPS</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D11 // GSPI2_MISO_FPS</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D12 // GSPI2_MOSI_FPS</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_J2, NONE, PLTRST, EDGE_SINGLE, NONE), // FPS_INT_N</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_J3, 1, PLTRST), // FPS_RST_N</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ //I2C</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C16 // I2C0_SDA</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C17 // I2C0_SCL</span><br><span style="color: hsl(120, 100%, 40%);">+ // Touch panel</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B18, 1, PLTRST), // I2C_TCH_PNL_PWREN</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_J0, UP_20K, PLTRST, EDGE_SINGLE, INVERT), // I2C_TCH_PNL_INT</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_J10, 1, PLTRST), // I2C_TCH_PNL_RST_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D4 // I2C3_SDA</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D23 // I2C3_SCL</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ //LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C3 // SML0_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C4 // SML0_DATA</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H3 // LAN_CLKREQ</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D2 // LAN_WAKE</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D9 // PM_SLP_WLAN_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D11 // LANPHY_EN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // M.2 BT</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_RF_KILL</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_C2, NONE, PLTRST, LEVEL, INVERT), // BT_UART_WAKE</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D5 // SSP2_SFRM_CNV_RF_RST</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D6 // SSP2_TXD_MODEM_CKREC</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_INT(GPP_D7, NONE, PLTRST, LEVEL), // SSP2_RXD</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_INT(GPP_D8, NONE, PLTRST, LEVEL), // SSP2_SCLK</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // M.2 SSD1</span><br><span style="color: hsl(120, 100%, 40%);">+ // De-assert RESET pin</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C14, 1, PLTRST), // SSD1_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_E1 // SSD1_DET</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_E5 // SSD1_SATA_Devsleep</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H1 // SSD1_CLKREQ</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_K8 // SSD1_PWREN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // M.2 SSD2</span><br><span style="color: hsl(120, 100%, 40%);">+ // De-assert RESET pin</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_C15, 1, PLTRST), // SSD2_RESET</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F1 // SSD2_PEDET_R</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H6 // SSD2_CLKREQ</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_K9 // SSD2_PWREN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // M.2 WiFi</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_B4, 1, DEEP), // WIFI_RF_KILL</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL), // WIFI_WAKE_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H0 // WIFI_CLREQ</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // PCIE Flex, X1, X4</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_B10 // PCIe FLEX</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_B8 // PCIE X1 CLKREQ</span><br><span style="color: hsl(120, 100%, 40%);">+ // De-assert RESET pin</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_F4, 1, PLTRST), // SLOT2_RST_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H5 // PCIE X4 CLKREQ</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H18 // SLOT2_PWREN</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_K18, NONE, PLTRST, LEVEL), // SLOT2_WAKE_N</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // PEG Slot</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F8 // PEG_SLOT_PWREN</span><br><span style="color: hsl(120, 100%, 40%);">+ // De-assert RESET pin</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_F9, 1, PLTRST), // PEG_SLOT_RST</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F12 // SLOT2_WAKE_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H2 // PCIE X4 CLKREQ</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // PM</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_B12 // PM_SLP_S0_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_B13 // PLT_RST_N</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Power management</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPD0 // PM_BATLOW_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPD1 // BC_ACOK</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPD3 // PM_PWRBTN_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPD4 // PM_SLP_S3_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPD5 // PM_SLP_S4_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPD6 // SLP_A_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPD8 // SUS_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPD10 // PM_SLP_S5_N</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_E8 // SATA_LED_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F6 // M.2_SSD2_HDD_DEVSLP</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F2 // SATA_ODD_PRSNT</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_K1, 1, PLTRST), // SATA_ODD_PWRGT_R</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_HIGH(GPP_K2, NONE, PLTRST, EDGE_SINGLE), // SATA_ODD_DA_N</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // SD Card</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G5, UP_20K, DEEP, GPIO), // GPP_G_5_SD3_CDB</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, GPIO), // GPP_G_7_SD3_WP</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Sensor</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_A12 // Sensor Header</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_A18 // Sensor Header</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_A19 // Sensor Header</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_A20 // Sensor Header</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_A21 // Sensor Header</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_A22 // Sensor Header</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_A23 // Sensor Header</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H19 // ISH_I2C0_SDA</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H20 // ISH_I2C0_SCL</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H21 // ISH_I2C1_SDA</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_H22 // ISH_I2C1_SCL</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Serial</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C20 // UART2_RXD</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C21 // UART2_TXD</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C22 // UART2_RTS</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C23 // UART2_CTS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // SMBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C0 // SMB_CLK</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_C1 // SMB_DATA</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_B0, UP_20K, DEEP, EDGE_SINGLE), // SPI_TPM_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // SPI Touch Panel</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_B14 // SPI1_TCH_PNL_PWREN</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D0 // SPI1_TCH_PNL_CS0_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D1 // SPI1_TCH_PNL_CLK_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D2 // SPI1_TCH_PNL_MISO</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D3 // SPI1_TCH_PNL_MOSI</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D15 // SPI1_TCH_PNL_INT_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D16 // SPI1_TCH_PNL_RST_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D21 // SPI1_TCH_PNL_IO2</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D22 // SPI1_TCH_PNL_IO3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // TBT</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H16, 1, PLTRST), // TBT_CIO_PWREN</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPO(GPP_H17, 0, PLTRST), // TBT_FORCE_PWR</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_SCI_LOW(GPP_H23, NONE, PLTRST, EDGE_SINGLE), // TBT_CIO_PLUG_EVENT_N</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // Touch pad</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_GPI_APIC(GPP_A16, NONE, PLTRST, LEVEL, INVERT), // TCH_PAD_INT_N</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D13 // I2C2_SDA</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_D14 // I2C2_SCL</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // USB</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_E9 // USB_OC0</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_E10 // USB_OC1</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_E11 // USB_OC2</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_E12 // USB_OC3</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F15 // USB_OC4</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F16 // USB_OC5</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F17 // USB_OC6</span><br><span style="color: hsl(120, 100%, 40%);">+ //GPP_F18 // USB_OC7</span><br><span> };</span><br><span> </span><br><span> /* Early pad configuration in bootblock */</span><br><span>diff --git a/src/soc/intel/coffeelake/acpi/gpio.asl b/src/soc/intel/coffeelake/acpi/gpio.asl</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index e20a47d..17c5487</span><br><span>--- a/src/soc/intel/coffeelake/acpi/gpio.asl</span><br><span>+++ b/src/soc/intel/coffeelake/acpi/gpio.asl</span><br><span>@@ -20,7 +20,7 @@</span><br><span> </span><br><span> Device (GPIO)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_HID, "INT34BB")</span><br><span style="color: hsl(120, 100%, 40%);">+ Name (_HID, "INT3450")</span><br><span> Name (_UID, 0)</span><br><span> Name (_DDN, "GPIO Controller")</span><br><span> </span><br><span>@@ -84,16 +84,16 @@</span><br><span> Method (GADD, 1, NotSerialized)</span><br><span> {</span><br><span> /* GPIO Community 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11)))</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23)))</span><br><span> {</span><br><span> Store (PID_GPIOCOM0, Local0)</span><br><span> Subtract (Arg0, GPP_A0, Local1)</span><br><span> }</span><br><span> /* GPIO Community 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPIO_RSVD_52)))</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_G7)))</span><br><span> {</span><br><span> Store (PID_GPIOCOM1, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- Subtract (Arg0, GPP_D0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_C0, Local1)</span><br><span> }</span><br><span> /* GPIO Community 2 */</span><br><span> If (LAnd (LGreaterEqual (Arg0, GPD0), LLessEqual (Arg0, GPD11)))</span><br><span>@@ -102,16 +102,16 @@</span><br><span> Subtract (Arg0, GPD0, Local1)</span><br><span> }</span><br><span> /* GPIO Community 3 */</span><br><span style="color: hsl(0, 100%, 40%);">- If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_78)))</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, GPP_F23)))</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- Store (PID_GPIOCOM1, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- Subtract (Arg0, HDA_BCLK, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (PID_GPIOCOM3, Local0)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_K0, Local1)</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- /* GPIO Community 04*/</span><br><span style="color: hsl(0, 100%, 40%);">- If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_67)))</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPIO Community 4*/</span><br><span style="color: hsl(120, 100%, 40%);">+ If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_J11)))</span><br><span> {</span><br><span> Store (PID_GPIOCOM4, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- Subtract (Arg0, GPP_C0, Local1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Subtract (Arg0, GPP_I0, Local1)</span><br><span> }</span><br><span> Store (PCRB (Local0), Local2)</span><br><span> Add (Local2, PAD_CFG_BASE, Local2)</span><br><span>diff --git a/src/soc/intel/coffeelake/gpio.c b/src/soc/intel/coffeelake/gpio.c</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index ff33cf8..cbb93d8</span><br><span>--- a/src/soc/intel/coffeelake/gpio.c</span><br><span>+++ b/src/soc/intel/coffeelake/gpio.c</span><br><span>@@ -16,7 +16,6 @@</span><br><span> #include <intelblocks/gpio.h></span><br><span> #include <intelblocks/pcr.h></span><br><span> #include <soc/pcr_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pmc.h></span><br><span> </span><br><span> static const struct reset_mapping rst_map[] = {</span><br><span> { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },</span><br><span>@@ -32,17 +31,14 @@</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cfl_community0_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_A0, GPIO_RSVD_0), /* GPP_A */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_B0, GPIO_RSVD_2), /* GPP_B */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPP_G0, GPP_G7), /* GPP_G */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP_A */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP_B */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cfl_community1_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPP_D0, GPIO_RSVD_12), /* GPP_D */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPP_F0, GPP_F23), /* GPP_F */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPP_H0, GPP_H23), /* GPP_H */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_D0, GPIO_RSVD_12, GPIO_RSVD_52), /* VGPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP_D */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_C0, GPP_G0, GPP_G7), /* GPP_G */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cfl_community2_groups[] = {</span><br><span>@@ -50,45 +46,45 @@</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cfl_community3_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(HDA_BCLK, GPIO_RSVD_68, GPIO_RSVD_78), /* CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_K0, GPP_K0, GPP_K23), /* GPP_K */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_K0, GPP_H0, GPP_H23), /* GPP_H */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_K0, GPP_E0, GPP_E12), /* GPP_E */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_K0, GPP_F0, GPP_F23), /* GPP_F */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_group cfl_community4_groups[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP_E */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPIO_RSVD_53, GPIO_RSVD_61), /* JTAG */</span><br><span style="color: hsl(0, 100%, 40%);">- INTEL_GPP(GPP_C0, GPIO_RSVD_62, GPIO_RSVD_67), /* HVMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_I0, GPP_I0, GPP_I14), /* GPP_I */</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL_GPP(GPP_I0, GPP_J0, GPP_J11), /* GPP_J */</span><br><span> };</span><br><span> </span><br><span> static const struct pad_community cfl_communities[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- { /* GPP A, B, G, SPI */</span><br><span style="color: hsl(120, 100%, 40%);">+ { /* GPP A, B */</span><br><span> .port = PID_GPIOCOM0,</span><br><span> .first_pad = GPP_A0,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPIO_RSVD_11,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_B23,</span><br><span> .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span> .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span> .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span> .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span> .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(0, 100%, 40%);">- .name = "GPP_ABG",</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_AB",</span><br><span> .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span> .reset_map = rst_map_com0,</span><br><span> .num_reset_vals = ARRAY_SIZE(rst_map_com0),</span><br><span> .groups = cfl_community0_groups,</span><br><span> .num_groups = ARRAY_SIZE(cfl_community0_groups),</span><br><span style="color: hsl(0, 100%, 40%);">- }, { /* GPP D, F, H, VGPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP C, D, G */</span><br><span> .port = PID_GPIOCOM1,</span><br><span style="color: hsl(0, 100%, 40%);">- .first_pad = GPP_D0,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPIO_RSVD_52,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_C0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_G7,</span><br><span> .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span> .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span> .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span> .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span> .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(0, 100%, 40%);">- .name = "GPP_DFH",</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_CDG",</span><br><span> .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span> .reset_map = rst_map,</span><br><span> .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span>@@ -110,33 +106,33 @@</span><br><span> .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span> .groups = cfl_community2_groups,</span><br><span> .num_groups = ARRAY_SIZE(cfl_community2_groups),</span><br><span style="color: hsl(0, 100%, 40%);">- }, { /* AZA, CPU */</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP K, H, E, F */</span><br><span> .port = PID_GPIOCOM3,</span><br><span style="color: hsl(0, 100%, 40%);">- .first_pad = HDA_BCLK,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPIO_RSVD_78,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_K0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_F23,</span><br><span> .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span> .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span> .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span> .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span> .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(0, 100%, 40%);">- .name = "GP_AC",</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_KHEF",</span><br><span> .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span> .reset_map = rst_map,</span><br><span> .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span> .groups = cfl_community3_groups,</span><br><span> .num_groups = ARRAY_SIZE(cfl_community3_groups),</span><br><span style="color: hsl(0, 100%, 40%);">- }, { /* GPP C, E, JTAG, HVMOS */</span><br><span style="color: hsl(120, 100%, 40%);">+ }, { /* GPP I, J */</span><br><span> .port = PID_GPIOCOM4,</span><br><span style="color: hsl(0, 100%, 40%);">- .first_pad = GPP_C0,</span><br><span style="color: hsl(0, 100%, 40%);">- .last_pad = GPIO_RSVD_67,</span><br><span style="color: hsl(120, 100%, 40%);">+ .first_pad = GPP_I0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .last_pad = GPP_J11,</span><br><span> .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,</span><br><span> .pad_cfg_base = PAD_CFG_BASE,</span><br><span> .host_own_reg_0 = HOSTSW_OWN_REG_0,</span><br><span> .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,</span><br><span> .gpi_smi_en_reg_0 = GPI_SMI_EN_0,</span><br><span> .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,</span><br><span style="color: hsl(0, 100%, 40%);">- .name = "GPP_CEJ",</span><br><span style="color: hsl(120, 100%, 40%);">+ .name = "GPP_IJ",</span><br><span> .acpi_path = "\\_SB.PCI0.GPIO",</span><br><span> .reset_map = rst_map,</span><br><span> .num_reset_vals = ARRAY_SIZE(rst_map),</span><br><span>@@ -154,15 +150,18 @@</span><br><span> const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)</span><br><span> {</span><br><span> static const struct pmc_to_gpio_route routes[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_A, GPP_A },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_B, GPP_B },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_C, GPP_C },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_D, GPP_D },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_E, GPP_E },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_F, GPP_F },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_G, GPP_G },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPP_H, GPP_H },</span><br><span style="color: hsl(0, 100%, 40%);">- { PMC_GPD, GPD },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_A, GPP_A },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_B, GPP_B },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_C, GPP_C },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_D, GPP_D },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_E, GPP_E },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_F, GPP_F },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_G, GPP_G },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_H, GPP_H },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_I, GPP_I },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_J, GPP_J },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPP_K, GPP_K },</span><br><span style="color: hsl(120, 100%, 40%);">+ { GPD, GPD },</span><br><span> };</span><br><span> *num = ARRAY_SIZE(routes);</span><br><span> return routes;</span><br><span>diff --git a/src/soc/intel/coffeelake/include/soc/gpio.h b/src/soc/intel/coffeelake/include/soc/gpio.h</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index 3c10d08..c56b1d3</span><br><span>--- a/src/soc/intel/coffeelake/include/soc/gpio.h</span><br><span>+++ b/src/soc/intel/coffeelake/include/soc/gpio.h</span><br><span>@@ -19,6 +19,6 @@</span><br><span> #include <soc/gpio_defs.h></span><br><span> #include <intelblocks/gpio.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define CROS_GPIO_DEVICE_NAME "INT34BB:00"</span><br><span style="color: hsl(120, 100%, 40%);">+#define CROS_GPIO_DEVICE_NAME "INT3450:00"</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/coffeelake/include/soc/gpio_defs.h b/src/soc/intel/coffeelake/include/soc/gpio_defs.h</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index d5731e5..ab35f8e</span><br><span>--- a/src/soc/intel/coffeelake/include/soc/gpio_defs.h</span><br><span>+++ b/src/soc/intel/coffeelake/include/soc/gpio_defs.h</span><br><span>@@ -240,12 +240,86 @@</span><br><span> #define GPP_H21_IRQ 0x5d</span><br><span> #define GPP_H22_IRQ 0x5e</span><br><span> #define GPP_H23_IRQ 0x5f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group I */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I0_IRQ 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I1_IRQ 0x19</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I2_IRQ 0x1a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I3_IRQ 0x1b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I4_IRQ 0x1c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I5_IRQ 0x1d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I6_IRQ 0x1e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I7_IRQ 0x1f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I8_IRQ 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I9_IRQ 0x21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I10_IRQ 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I11_IRQ 0x23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I12_IRQ 0x24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I13_IRQ 0x25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I14_IRQ 0x26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I15_IRQ 0x27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I16_IRQ 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I17_IRQ 0x29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I18_IRQ 0x2a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I19_IRQ 0x2b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I20_IRQ 0x2c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I21_IRQ 0x2d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I22_IRQ 0x2e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I23_IRQ 0x2f</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group J */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J0_IRQ 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J1_IRQ 0x31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J2_IRQ 0x32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J3_IRQ 0x33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J4_IRQ 0x34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J5_IRQ 0x35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J6_IRQ 0x36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J7_IRQ 0x37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J8_IRQ 0x38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J9_IRQ 0x39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J10_IRQ 0x3a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J11_IRQ 0x3b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J12_IRQ 0x3c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J13_IRQ 0x3d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J14_IRQ 0x3e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J15_IRQ 0x3f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J16_IRQ 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J17_IRQ 0x41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J18_IRQ 0x42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J19_IRQ 0x43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J20_IRQ 0x44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J21_IRQ 0x45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J22_IRQ 0x46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J23_IRQ 0x47</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group K */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K0_IRQ 0x48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K1_IRQ 0x49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K2_IRQ 0x4a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K3_IRQ 0x4b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K4_IRQ 0x4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K5_IRQ 0x4d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K6_IRQ 0x4e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K7_IRQ 0x4f</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K8_IRQ 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K9_IRQ 0x51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K10_IRQ 0x52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K11_IRQ 0x53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K12_IRQ 0x54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K13_IRQ 0x55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K14_IRQ 0x56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K15_IRQ 0x57</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K16_IRQ 0x58</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K17_IRQ 0x59</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K18_IRQ 0x5a</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K19_IRQ 0x5b</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K20_IRQ 0x5c</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K21_IRQ 0x5d</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K22_IRQ 0x5e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K23_IRQ 0x5f</span><br><span> /* Register defines. */</span><br><span> #define GPIO_MISCCFG 0x10</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPE_DW_SHIFT 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPE_DW_MASK 0xfff00</span><br><span style="color: hsl(0, 100%, 40%);">-#define HOSTSW_OWN_REG_0 0xb0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_DW_SHIFT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_DW_MASK 0xfff00</span><br><span style="color: hsl(120, 100%, 40%);">+#define HOSTSW_OWN_REG_0 0xc0</span><br><span> #define GPI_SMI_STS_0 0x180</span><br><span> #define GPI_SMI_EN_0 0x1A0</span><br><span> #define PAD_CFG_BASE 0x600</span><br><span>diff --git a/src/soc/intel/coffeelake/include/soc/gpio_soc_defs.h b/src/soc/intel/coffeelake/include/soc/gpio_soc_defs.h</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index 67b34dc..37db625</span><br><span>--- a/src/soc/intel/coffeelake/include/soc/gpio_soc_defs.h</span><br><span>+++ b/src/soc/intel/coffeelake/include/soc/gpio_soc_defs.h</span><br><span>@@ -24,21 +24,17 @@</span><br><span> */</span><br><span> #define GPP_A 0</span><br><span> #define GPP_B 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_SPI 3</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D 4</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K 5</span><br><span> #define GPP_H 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_VGPIO 7</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD 9</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_AZA 0xA</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_CPU 0xB</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C 0xC</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E 0xD</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_JTAG 0xE</span><br><span style="color: hsl(0, 100%, 40%);">-#define GROUP_HVMOS 0xF</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_NUM_GROUPS 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E 7</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J 10</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_NUM_GROUPS 11</span><br><span> #define GPIO_MAX_NUM_PER_GROUP 24</span><br><span> </span><br><span> /*</span><br><span>@@ -70,286 +66,242 @@</span><br><span> #define GPP_A21 21</span><br><span> #define GPP_A22 22</span><br><span> #define GPP_A23 23</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_0 24</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Group B */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B0 25</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B1 26</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B2 27</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B3 28</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B4 29</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B5 30</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B6 31</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B7 32</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B8 33</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B9 34</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B10 35</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B11 36</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B12 37</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B13 38</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B14 39</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B15 40</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B16 41</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B17 42</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B18 43</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B19 44</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B20 45</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B21 46</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B22 47</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_B23 48</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_1 49</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_2 50</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group G */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G0 51</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G1 52</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G2 53</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G3 54</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G4 55</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G5 56</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G6 57</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_G7 58</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group SPI */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_3 59</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_4 60</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_5 61</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_6 62</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_7 63</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_8 64</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_9 65</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_10 66</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_11 67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B0 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B1 25</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B2 26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B3 27</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B4 28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B5 29</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B6 30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B7 31</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B8 32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B9 33</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B10 34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B11 35</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B12 36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B13 37</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B14 38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B15 39</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B16 40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B17 41</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B18 42</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B19 43</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B20 44</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B21 45</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B22 46</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_B23 47</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM0_PADS (GPIO_RSVD_11 - GPP_A0 + 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group D */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D0 68</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D1 69</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D2 70</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D3 71</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D4 72</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D5 73</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D6 74</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D7 75</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D8 76</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D9 77</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D10 78</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D11 79</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D12 80</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D13 81</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D14 82</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D15 83</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D16 84</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D17 85</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D18 86</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D19 87</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D20 88</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D21 89</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D22 90</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_D23 91</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_12 92</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group F */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F0 93</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F1 94</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F2 95</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F3 96</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F4 97</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F5 98</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F6 99</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F7 100</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F8 101</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F9 102</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F10 103</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F11 104</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F12 105</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F13 106</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F14 107</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F15 108</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F16 109</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F17 110</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F18 111</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F19 112</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F20 113</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F21 114</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F22 115</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_F23 116</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group H */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H0 117</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H1 118</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H2 119</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H3 120</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H4 121</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H5 122</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H6 123</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H7 124</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H8 125</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H9 126</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H10 127</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H11 128</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H12 129</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H13 130</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H14 131</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H15 132</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H16 133</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H17 134</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H18 135</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H19 136</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H20 137</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H21 138</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H22 139</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_H23 140</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group VGOIO */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_13 141</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_14 142</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_15 143</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_16 144</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_17 145</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_18 146</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_19 147</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_20 148</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_21 149</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_22 150</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_23 151</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_24 152</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_25 153</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_26 154</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_27 155</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_28 156</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_29 157</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_30 158</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_31 159</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_32 160</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_33 161</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_34 162</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_35 163</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_36 164</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_37 165</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_38 166</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_39 167</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_40 168</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_41 169</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_42 170</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_43 171</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_44 172</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_45 173</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_46 174</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_47 175</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_48 176</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_49 177</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_50 178</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_51 179</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_52 180</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM1_PADS (GPIO_RSVD_52 - GPP_D0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM0_PADS (GPP_B23 - GPP_A0 + 1)</span><br><span> </span><br><span> /* Group C */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C0 181</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C1 182</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C2 183</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C3 184</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C4 185</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C5 186</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C6 187</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C7 188</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C8 189</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C9 190</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C10 191</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C11 192</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C12 193</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C13 194</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C14 195</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C15 196</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C16 197</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C17 198</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C18 199</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C19 200</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C20 201</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C21 202</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C22 203</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_C23 204</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group E */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E0 205</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E1 206</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E2 207</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E3 208</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E4 209</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E5 210</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E6 211</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E7 212</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E8 213</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E9 214</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E10 215</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E11 216</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E12 217</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E13 218</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E14 219</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E15 220</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E16 221</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E17 222</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E18 223</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E19 224</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E20 225</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E21 226</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E22 227</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_E23 228</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group Jtag */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_53 229</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_54 230</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_55 231</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_56 232</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_57 233</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_58 234</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_59 235</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_60 236</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_61 237</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group HVMOS */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_62 238</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_63 239</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_64 240</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_65 241</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_66 242</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_67 243</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C0 48</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C1 49</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C2 50</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C3 51</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C4 52</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C5 53</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C6 54</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C7 55</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C8 56</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C9 57</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C10 58</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C11 59</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C12 60</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C13 61</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C14 62</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C15 63</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C16 64</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C17 65</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C18 66</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C19 67</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C20 68</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C21 69</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C22 70</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_C23 71</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM4_PADS (GPIO_RSVD_67 - GPP_C0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group D */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D0 72</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D1 73</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D2 74</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D3 75</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D4 76</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D5 77</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D6 78</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D7 79</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D8 80</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D9 81</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D10 82</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D11 83</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D12 84</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D13 85</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D14 86</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D15 87</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D16 88</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D17 89</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D18 90</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D19 91</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D20 92</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D21 93</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D22 94</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_D23 95</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group G */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G0 96</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G1 97</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G2 98</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G3 99</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G4 100</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G5 101</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G6 102</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_G7 103</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM1_PADS (GPP_G7 - GPP_C0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group K */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K0 104</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K1 105</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K2 106</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K3 107</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K4 108</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K5 109</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K6 110</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K7 111</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K8 112</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K9 113</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K10 114</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K11 115</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K12 116</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K13 117</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K14 118</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K15 119</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K16 120</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K17 121</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K18 122</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K19 123</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K20 124</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K21 125</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K22 126</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_K23 127</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group H */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H0 128</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H1 129</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H2 130</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H3 131</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H4 132</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H5 133</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H6 134</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H7 135</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H8 136</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H9 137</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H10 138</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H11 139</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H12 140</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H13 141</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H14 142</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H15 143</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H16 144</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H17 145</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H18 146</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H19 147</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H20 148</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H21 149</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H22 150</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_H23 151</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group E */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E0 152</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E1 153</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E2 154</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E3 155</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E4 156</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E5 157</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E6 158</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E7 159</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E8 160</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E9 161</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E10 162</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E11 163</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_E12 164</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group F */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F0 165</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F1 166</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F2 167</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F3 168</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F4 169</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F5 170</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F6 171</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F7 172</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F8 173</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F9 174</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F10 175</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F11 176</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F12 177</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F13 178</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F14 179</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F15 180</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F16 181</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F17 182</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F18 183</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F19 184</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F20 185</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F21 186</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F22 187</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_F23 188</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM3_PADS (GPP_F23 - GPP_K0 + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group I */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I0 189</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I1 190</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I2 191</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I3 192</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I4 193</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I5 194</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I6 195</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I7 196</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I8 197</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I9 198</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I10 199</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I11 200</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I12 201</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I13 202</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_I14 203</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Group J */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J0 204</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J1 205</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J2 206</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J3 207</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J4 208</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J5 209</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J6 210</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J7 211</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J8 212</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J9 213</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J10 214</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_J11 215</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NUM_GPIO_COM4_PADS (GPP_J11 - GPP_I0 + 1)</span><br><span> </span><br><span> /* Group GPD */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD0 244</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD1 245</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD2 246</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD3 247</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD4 248</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD5 249</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD6 250</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD7 251</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD8 252</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD9 253</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD10 254</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPD11 255</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD0 216</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD1 217</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD2 218</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD3 219</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD4 220</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD5 221</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD6 222</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD7 223</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD8 224</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD9 225</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD10 226</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPD11 227</span><br><span> </span><br><span> #define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group AZA */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_BCLK 256</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_RSTB 257</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_SYNC 258</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_SDO 259</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_SDI_0 260</span><br><span style="color: hsl(0, 100%, 40%);">-#define HDA_SDI_1 261</span><br><span style="color: hsl(0, 100%, 40%);">-#define SSP1_SFRM 262</span><br><span style="color: hsl(0, 100%, 40%);">-#define SSP1_TXD 263</span><br><span style="color: hsl(0, 100%, 40%);">-/* Group CPU */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_68 264</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_69 265</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_70 266</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_71 267</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_72 268</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_73 269</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_74 270</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_75 271</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_76 272</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_77 273</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_RSVD_78 274</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define NUM_GPIO_COM3_PADS (GPIO_RSVD_78 - HDA_BCLK + 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define TOTAL_PADS 275</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOTAL_PADS (GPD11 + 1)</span><br><span> #endif</span><br><span></span><br></pre><p>To view, visit <a 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3acf0a0e3101eadb3464baf8e1a7ba5b32804777 </div>
<div style="display:none"> Gerrit-Change-Number: 25241 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kin Wai Ng <kin.wai.ng@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Naresh Solanki <naresh.solanki@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>