<p>Kin Wai Ng would like Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela and Rizwan Qureshi to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/25238">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/coffeelake_rvp: Enable PCIE X1, X4 and X16 slot<br><br>Refer schematic:<br>GPP_B_8_SRCCLKREQB_3<br>GPP_B_9_SRCCLKREQB_4<br>GPP_H_2_SRCCLKREQB_8<br><br>Change-Id: I95bb69d27b595669e4790fb73de60e724f49dc83<br>Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com><br>---<br>M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb<br>1 file changed, 10 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/25238/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>index f84400d..a6d9a6e 100755</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>@@ -62,13 +62,20 @@</span><br><span>    register "PcieRpEnable[11]" = "1"</span><br><span>        register "PcieRpEnable[12]" = "1"</span><br><span>        register "PcieRpEnable[13]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[14]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[15]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[20]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[21]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[22]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[23]" = "1"</span><br><span> </span><br><span>    register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"</span><br><span>       register "PcieClkSrcUsage[1]" = "8"</span><br><span>      register "PcieClkSrcUsage[2]" = "0xff" #NOT_USE</span><br><span style="color: hsl(0, 100%, 40%);">-     register "PcieClkSrcUsage[3]" = "14"</span><br><span style="color: hsl(0, 100%, 40%);">-        register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"</span><br><span style="color: hsl(120, 100%, 40%);">+        register "PcieClkSrcUsage[3]" = "0x6"</span><br><span style="color: hsl(120, 100%, 40%);">+     register "PcieClkSrcUsage[4]" = "0x18"</span><br><span>   register "PcieClkSrcUsage[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+       register "PcieClkSrcUsage[8]" = "0x40"</span><br><span>   register "PcieClkSrcUsage[9]" = "PCIE_CLK_LAN"</span><br><span> </span><br><span>       register "PcieClkSrcClkReq[0]" = "0"</span><br><span>@@ -77,6 +84,7 @@</span><br><span>         register "PcieClkSrcClkReq[3]" = "3"</span><br><span>     register "PcieClkSrcClkReq[4]" = "4"</span><br><span>     register "PcieClkSrcClkReq[5]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+      register "PcieClkSrcClkReq[8]" = "8"</span><br><span>     register "PcieClkSrcClkReq[9]" = "9"</span><br><span> </span><br><span>         # Enable "Intel Speed Shift Technology"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25238">change 25238</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25238"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I95bb69d27b595669e4790fb73de60e724f49dc83 </div>
<div style="display:none"> Gerrit-Change-Number: 25238 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kin Wai Ng <kin.wai.ng@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Naresh Solanki <naresh.solanki@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>