<p>Kin Wai Ng would like Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela and Rizwan Qureshi to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/25234">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/coffeelake_rvp: Fix I2C4, I2C5 and UART2 CFL-H specific device<br><br>1. I2C4, I2C5 not found in CFL-H.<br>2. Add UART2 device<br><br>Change-Id: Ic00782f2a186b4f1fff169044e25246e1e13248b<br>Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com><br>---<br>M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb<br>M src/soc/intel/coffeelake/chip.c<br>M src/soc/intel/coffeelake/i2c.c<br>M src/soc/intel/coffeelake/include/soc/pci_devs.h<br>4 files changed, 3 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/25234/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>index 0a18432..fe6736e 100755</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb</span><br><span>@@ -117,9 +117,7 @@</span><br><span> device pci 16.4 off end # Management Engine Interface 3</span><br><span> device pci 16.5 off end # Management Engine Interface 4</span><br><span> device pci 17.0 off end # SATA</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.0 on end # I2C #4</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.1 off end # I2C #5</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 19.2 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on end # UART #2</span><br><span> device pci 1a.0 on end # eMMC</span><br><span> device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1</span><br><span> device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN</span><br><span>diff --git a/src/soc/intel/coffeelake/chip.c b/src/soc/intel/coffeelake/chip.c</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index cf6a334..9819ee1</span><br><span>--- a/src/soc/intel/coffeelake/chip.c</span><br><span>+++ b/src/soc/intel/coffeelake/chip.c</span><br><span>@@ -51,8 +51,6 @@</span><br><span> case PCH_DEVFN_CSE_3: return "CSE3";</span><br><span> case PCH_DEVFN_SATA: return "SATA";</span><br><span> case PCH_DEVFN_UART2: return "UAR2";</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_I2C4: return "I2C4";</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_I2C5: return "I2C5";</span><br><span> case PCH_DEVFN_PCIE1: return "RP01";</span><br><span> case PCH_DEVFN_PCIE2: return "RP02";</span><br><span> case PCH_DEVFN_PCIE3: return "RP03";</span><br><span>@@ -104,8 +102,6 @@</span><br><span> PCH_DEVFN_I2C1,</span><br><span> PCH_DEVFN_I2C2,</span><br><span> PCH_DEVFN_I2C3,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_I2C4,</span><br><span style="color: hsl(0, 100%, 40%);">- PCH_DEVFN_I2C5,</span><br><span> PCH_DEVFN_GSPI0,</span><br><span> PCH_DEVFN_GSPI1,</span><br><span> PCH_DEVFN_GSPI2,</span><br><span>diff --git a/src/soc/intel/coffeelake/i2c.c b/src/soc/intel/coffeelake/i2c.c</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index df46ef3..8536fc0</span><br><span>--- a/src/soc/intel/coffeelake/i2c.c</span><br><span>+++ b/src/soc/intel/coffeelake/i2c.c</span><br><span>@@ -53,10 +53,6 @@</span><br><span> return 2;</span><br><span> case PCH_DEVFN_I2C3:</span><br><span> return 3;</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_I2C4:</span><br><span style="color: hsl(0, 100%, 40%);">- return 4;</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_I2C5:</span><br><span style="color: hsl(0, 100%, 40%);">- return 5;</span><br><span> }</span><br><span> return -1;</span><br><span> }</span><br><span>@@ -72,10 +68,6 @@</span><br><span> return PCH_DEVFN_I2C2;</span><br><span> case 3:</span><br><span> return PCH_DEVFN_I2C3;</span><br><span style="color: hsl(0, 100%, 40%);">- case 4:</span><br><span style="color: hsl(0, 100%, 40%);">- return PCH_DEVFN_I2C4;</span><br><span style="color: hsl(0, 100%, 40%);">- case 5:</span><br><span style="color: hsl(0, 100%, 40%);">- return PCH_DEVFN_I2C5;</span><br><span> }</span><br><span> return -1;</span><br><span> }</span><br><span>diff --git a/src/soc/intel/coffeelake/include/soc/pci_devs.h b/src/soc/intel/coffeelake/include/soc/pci_devs.h</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index d98f81f..6b66cbc</span><br><span>--- a/src/soc/intel/coffeelake/include/soc/pci_devs.h</span><br><span>+++ b/src/soc/intel/coffeelake/include/soc/pci_devs.h</span><br><span>@@ -100,12 +100,8 @@</span><br><span> #define PCH_DEV_SATA _PCH_DEV(SATA, 0)</span><br><span> </span><br><span> #define PCH_DEV_SLOT_SIO2 0x19</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_DEV_UART2 _PCH_DEV(SIO2, 0)</span><br><span> </span><br><span> #define PCH_DEV_SLOT_STORAGE 0x1A</span><br><span> #define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25234">change 25234</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic00782f2a186b4f1fff169044e25246e1e13248b </div>
<div style="display:none"> Gerrit-Change-Number: 25234 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kin Wai Ng <kin.wai.ng@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Naresh Solanki <naresh.solanki@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>