<p>Kin Wai Ng would like Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela and Rizwan Qureshi to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/25229">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/coffeelake_rvp: Modified memory dimm settings<br><br>1. Hardcoded SPD Addresses<br>2. Modified memory dimm values to suit CFL-H RVP11<br><br>Change-Id: I4011de101d9a35e4735fc8491015aa56ebe80e7e<br>Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com><br>---<br>M src/mainboard/intel/coffeelake_rvp/romstage.c<br>M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c<br>2 files changed, 16 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/25229/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index e0699da..a2c719b</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/romstage.c</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/romstage.c</span><br><span>@@ -36,8 +36,8 @@</span><br><span> mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);</span><br><span> mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->DqPinsInterleaved = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->DqPinsInterleaved = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA/CHB */</span><br><span> mem_cfg->ECT = 1; /* Early Command Training Enabled */</span><br><span> spd_index = 2;</span><br><span> </span><br><span>@@ -51,4 +51,9 @@</span><br><span> mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);</span><br><span> mem_cfg->RefClk = 0; /* Auto Select CLK freq */</span><br><span> mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[0] = 0xA0;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[1] = 0xA2;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[2] = 0xA4;</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_cfg->SpdAddressTable[3] = 0xA6;</span><br><span> }</span><br><span>diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c</span><br><span>old mode 100644</span><br><span>new mode 100755</span><br><span>index 4e2f31f..ece6b6c</span><br><span>--- a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c</span><br><span>+++ b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c</span><br><span>@@ -23,8 +23,8 @@</span><br><span> {</span><br><span> /* DQ byte map Ch0 */</span><br><span> const u8 dq_map[12] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 ,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 };</span><br><span> </span><br><span> memcpy(dq_map_ptr, dq_map, sizeof(dq_map));</span><br><span> }</span><br><span>@@ -32,8 +32,8 @@</span><br><span> void mainboard_fill_dq_map_ch1(void *dq_map_ptr)</span><br><span> {</span><br><span> const u8 dq_map[12] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 };</span><br><span> </span><br><span> memcpy(dq_map_ptr, dq_map, sizeof(dq_map));</span><br><span> }</span><br><span>@@ -41,27 +41,17 @@</span><br><span> void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)</span><br><span> {</span><br><span> /* DQS CPU<>DRAM map Ch0 */</span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map_h[8] = { 0, 1, 3, 2, 4, 5, 6, 7 };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h));</span><br><span> }</span><br><span> </span><br><span> void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)</span><br><span> {</span><br><span> /* DQS CPU<>DRAM map Ch1 */</span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };</span><br><span style="color: hsl(120, 100%, 40%);">+ const u8 dqs_map_h[8] = { 1, 0, 4, 5, 2, 3, 6, 7 };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));</span><br><span style="color: hsl(0, 100%, 40%);">- else</span><br><span style="color: hsl(0, 100%, 40%);">- memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));</span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h));</span><br><span> }</span><br><span> </span><br><span> void mainboard_fill_rcomp_res_data(void *rcomp_ptr)</span><br><span>@@ -75,7 +65,7 @@</span><br><span> {</span><br><span> /* Rcomp target */</span><br><span> static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {</span><br><span style="color: hsl(0, 100%, 40%);">- 80, 40, 40, 40, 30 };</span><br><span style="color: hsl(120, 100%, 40%);">+ 100, 33, 32, 33, 28 };</span><br><span> </span><br><span> memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25229">change 25229</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4011de101d9a35e4735fc8491015aa56ebe80e7e </div>
<div style="display:none"> Gerrit-Change-Number: 25229 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kin Wai Ng <kin.wai.ng@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aamir Bohra <aamir.bohra@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Naresh Solanki <naresh.solanki@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>