<p>Srinidhi N Kaushik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25247">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/intel:Update FSP Header files per v2.0.0<br><br>Update FSP header files to match GLK FSP Reference Code Release v2.0.0<br><br>Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5<br>Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>2 files changed, 73 insertions(+), 118 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/25247/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h</span><br><span>index acbc596..4559e22 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h</span><br><span>@@ -1,6 +1,6 @@</span><br><span> /** @file</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span> </span><br><span> Redistribution and use in source and binary forms, with or without modification,</span><br><span> are permitted provided that the following conditions are met:</span><br><span>@@ -52,6 +52,9 @@</span><br><span> #define MAX_SPD_SAVE 29</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_LPDDR4 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define MRC_DDR_TYPE_DDR4 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> //</span><br><span> // MRC version description.</span><br><span> //</span><br><span>@@ -805,11 +808,9 @@</span><br><span> **/</span><br><span> UINT32 OemLoadingBase;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0120 - OEM File Name to Load</span><br><span style="color: hsl(0, 100%, 40%);">- Specify a file name to load from CSE file system after memory is available. Empty</span><br><span style="color: hsl(0, 100%, 40%);">- indicates no file needs to be loaded.</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0120</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 OemFileName[16];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Reserved[16];</span><br><span> </span><br><span> /** Offset 0x0130</span><br><span> **/</span><br><span>@@ -962,37 +963,41 @@</span><br><span> **/</span><br><span> VOID* VariableNvsBufferPtr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0164</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0164 - PERST pin for RootPort 0</span><br><span style="color: hsl(120, 100%, 40%);">+ Address for PERST pin for Rootport 0. For Intel RVP, address of N_GPIO_105. 0x00C507D0(Default).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 RootPort0Perst;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0168 - PERST pin for RootPort 1</span><br><span style="color: hsl(120, 100%, 40%);">+ Address for PERST pin for Rootport 1. For Intel RVP, address of A_GPIO_163. 0x00C90670(Default).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 RootPort1Perst;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x016C - PERST pin for RootPort 2</span><br><span style="color: hsl(120, 100%, 40%);">+ Address for PERST pin for Rootport 2. For Intel RVP, address of N_GPIO_137. 0x00C509D0(Default).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 RootPort2Perst;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0170 - PERST pin for RootPort 3</span><br><span style="color: hsl(120, 100%, 40%);">+ Address for PERST pin for Rootport 3.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 RootPort3Perst;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0174 - PERST pin for RootPort 4</span><br><span style="color: hsl(120, 100%, 40%);">+ Address for PERST pin for Rootport 4. For Intel RVP, address of SCC_GPIO_210. 0x00C806D0(Default).</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 RootPort4Perst;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0178 - PERST pin for RootPort 5</span><br><span style="color: hsl(120, 100%, 40%);">+ Address for PERST pin for Rootport 5.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 RootPort5Perst;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x017C</span><br><span> **/</span><br><span> UINT8 ReservedFspmUpd[4];</span><br><span> } FSP_M_CONFIG;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Fsp M Test Configuration</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0168</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Signature;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x016C</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspmTestUpd[20];</span><br><span style="color: hsl(0, 100%, 40%);">-} FSP_M_TEST_CONFIG;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Fsp M Restricted Configuration</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0180</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Signature;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0184</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspmRestrictedUpd[124];</span><br><span style="color: hsl(0, 100%, 40%);">-} FSP_M_RESTRICTED_CONFIG;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /** Fsp M UPD Configuration</span><br><span> **/</span><br><span> typedef struct {</span><br><span>@@ -1009,17 +1014,9 @@</span><br><span> **/</span><br><span> FSP_M_CONFIG FspmConfig;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0168</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_M_TEST_CONFIG FspmTestConfig;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /** Offset 0x0180</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0200</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace1[6];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace1[134];</span><br><span> </span><br><span> /** Offset 0x0206</span><br><span> **/</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>index e4839e0..cc50058 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>@@ -1,6 +1,6 @@</span><br><span> /** @file</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span> </span><br><span> Redistribution and use in source and binary forms, with or without modification,</span><br><span> are permitted provided that the following conditions are met:</span><br><span>@@ -1672,74 +1672,40 @@</span><br><span> **/</span><br><span> UINT16 HgSubSystemId;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0388</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0388 - USB Per Port HS Preemphasis Bias</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV,</span><br><span style="color: hsl(120, 100%, 40%);">+ 100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port.</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspsUpd[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfePetxiset[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0390 - USB Per Port HS Transmitter Bias</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port HS Transmitter Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV,</span><br><span style="color: hsl(120, 100%, 40%);">+ 100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfeTxiset[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0398 - USB Per Port HS Transmitter Emphasis</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,</span><br><span style="color: hsl(120, 100%, 40%);">+ 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfePredeemp[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03A0 - USB Per Port Half Bit Pre-emphasis</span><br><span style="color: hsl(120, 100%, 40%);">+ USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.</span><br><span style="color: hsl(120, 100%, 40%);">+ One byte for each port.</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Usb2AfePehalfbit[8];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03A8 - Intel Processor Trace output Scheme method</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Processor Trace output Scheme method 0:Single Range Output (Default) 1. ToPA Output</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ProcessorTraceOutputScheme;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03A9</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspsUpd[7];</span><br><span> } FSP_S_CONFIG;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Fsp S Test Configuration</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0390</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Signature;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0394</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspsTestUpd[12];</span><br><span style="color: hsl(0, 100%, 40%);">-} FSP_S_TEST_CONFIG;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Fsp S Restricted Configuration</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03A0</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Signature;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03A4 - Selective enable SGX</span><br><span style="color: hsl(0, 100%, 40%);">- Selective enable SGX. 0xFFFF(Default).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 SelectiveEnableSgx;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03A6 - SGX debug mode</span><br><span style="color: hsl(0, 100%, 40%);">- Select SGX mode. 0:Disable(default), 1:Enable</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Disable(default), 1:Enable</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SgxDebugMode;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03A7 - SGX Launch Control Policy Mode</span><br><span style="color: hsl(0, 100%, 40%);">- Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)</span><br><span style="color: hsl(0, 100%, 40%);">- 0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SgxLcp;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03A8 - LE KeyHash0</span><br><span style="color: hsl(0, 100%, 40%);">- LE KeyHash0. 0x0(Default).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 SgxLePubKeyHash0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03B0 - LE KeyHash1</span><br><span style="color: hsl(0, 100%, 40%);">- LE KeyHash1. 0x0(Default).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 SgxLePubKeyHash1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03B8 - LE KeyHash2</span><br><span style="color: hsl(0, 100%, 40%);">- LE KeyHash2. 0x0(Default).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 SgxLePubKeyHash2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03C0 - LE KeyHash3</span><br><span style="color: hsl(0, 100%, 40%);">- LE KeyHash3. 0x0(Default).</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT64 SgxLePubKeyHash3;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03C8</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspsRestrictedUpd[8];</span><br><span style="color: hsl(0, 100%, 40%);">-} FSP_S_RESTRICTED_CONFIG;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /** Fsp S UPD Configuration</span><br><span> **/</span><br><span> typedef struct {</span><br><span>@@ -1752,19 +1718,11 @@</span><br><span> **/</span><br><span> FSP_S_CONFIG FspsConfig;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0390</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03B0</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_S_TEST_CONFIG FspsTestConfig;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace7[78];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03A0</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03D0</span><br><span style="color: hsl(0, 100%, 40%);">-**/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace7[6];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03D6</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03FE</span><br><span> **/</span><br><span> UINT16 UpdTerminator;</span><br><span> } FSPS_UPD;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25247">change 25247</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25247"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5 </div>
<div style="display:none"> Gerrit-Change-Number: 25247 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> </div>