<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25197">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/braswell: Save/restore GMA OpRegion address<br><br>Add global/ACPI nvs variables required for IGD OpRegion.<br>Add functions necessary to save the ACPI OpRegion table<br>address in ASLB, and restore table address upon S3 resume.<br><br>Implementation modeled on existing Baytrail code.<br><br>Test: boot Windows 10 on google/edgar with Tianocore payload and<br>GOP display init, observe display driver loaded and functional,<br>display not black screen when resuming from S3 suspend.<br><br>Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/braswell/acpi.c<br>M src/soc/intel/braswell/acpi/globalnvs.asl<br>M src/soc/intel/braswell/gfx.c<br>M src/soc/intel/braswell/include/soc/nvs.h<br>4 files changed, 98 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/25197/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c</span><br><span>index 61ad03d..9ac5574c 100644</span><br><span>--- a/src/soc/intel/braswell/acpi.c</span><br><span>+++ b/src/soc/intel/braswell/acpi.c</span><br><span>@@ -486,6 +486,7 @@</span><br><span> struct acpi_rsdp *rsdp)</span><br><span> {</span><br><span> acpi_header_t *ssdt2;</span><br><span style="color: hsl(120, 100%, 40%);">+ global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);</span><br><span> </span><br><span> current = acpi_write_hpet(device, current, rsdp);</span><br><span> current = acpi_align_current(current);</span><br><span>@@ -496,6 +497,8 @@</span><br><span> printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");</span><br><span> opregion = (igd_opregion_t *)current;</span><br><span> intel_gma_init_igd_opregion(opregion);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->aslb = (u32)opregion;</span><br><span> update_igd_opregion(opregion);</span><br><span> current += sizeof(igd_opregion_t);</span><br><span> current = acpi_align_current(current);</span><br><span>diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl</span><br><span>index a53834a..c0b0b8d 100644</span><br><span>--- a/src/soc/intel/braswell/acpi/globalnvs.asl</span><br><span>+++ b/src/soc/intel/braswell/acpi/globalnvs.asl</span><br><span>@@ -71,6 +71,48 @@</span><br><span> TOLM, 32, /* 0x34 - Top of Low Memory */</span><br><span> CBMC, 32, /* 0x38 - coreboot mem console pointer */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* IGD OpRegion */</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0xb4),</span><br><span style="color: hsl(120, 100%, 40%);">+ ASLB, 32, // 0xb4 - IGD OpRegion Base Address</span><br><span style="color: hsl(120, 100%, 40%);">+ IBTT, 8, // 0xb8 - IGD boot panel device</span><br><span style="color: hsl(120, 100%, 40%);">+ IPAT, 8, // 0xb9 - IGD panel type cmos option</span><br><span style="color: hsl(120, 100%, 40%);">+ ITVF, 8, // 0xba - IGD TV format cmos option</span><br><span style="color: hsl(120, 100%, 40%);">+ ITVM, 8, // 0xbb - IGD TV minor format option</span><br><span style="color: hsl(120, 100%, 40%);">+ IPSC, 8, // 0xbc - IGD panel scaling</span><br><span style="color: hsl(120, 100%, 40%);">+ IBLC, 8, // 0xbd - IGD BLC config</span><br><span style="color: hsl(120, 100%, 40%);">+ IBIA, 8, // 0xbe - IGD BIA config</span><br><span style="color: hsl(120, 100%, 40%);">+ ISSC, 8, // 0xbf - IGD SSC config</span><br><span style="color: hsl(120, 100%, 40%);">+ I409, 8, // 0xc0 - IGD 0409 modified settings</span><br><span style="color: hsl(120, 100%, 40%);">+ I509, 8, // 0xc1 - IGD 0509 modified settings</span><br><span style="color: hsl(120, 100%, 40%);">+ I609, 8, // 0xc2 - IGD 0609 modified settings</span><br><span style="color: hsl(120, 100%, 40%);">+ I709, 8, // 0xc3 - IGD 0709 modified settings</span><br><span style="color: hsl(120, 100%, 40%);">+ IDMM, 8, // 0xc4 - IGD Power conservation feature</span><br><span style="color: hsl(120, 100%, 40%);">+ IDMS, 8, // 0xc5 - IGD DVMT memory size</span><br><span style="color: hsl(120, 100%, 40%);">+ IF1E, 8, // 0xc6 - IGD function 1 enable</span><br><span style="color: hsl(120, 100%, 40%);">+ HVCO, 8, // 0xc7 - IGD HPLL VCO</span><br><span style="color: hsl(120, 100%, 40%);">+ NXD1, 32, // 0xc8 - IGD _DGS next DID1</span><br><span style="color: hsl(120, 100%, 40%);">+ NXD2, 32, // 0xcc - IGD _DGS next DID2</span><br><span style="color: hsl(120, 100%, 40%);">+ NXD3, 32, // 0xd0 - IGD _DGS next DID3</span><br><span style="color: hsl(120, 100%, 40%);">+ NXD4, 32, // 0xd4 - IGD _DGS next DID4</span><br><span style="color: hsl(120, 100%, 40%);">+ NXD5, 32, // 0xd8 - IGD _DGS next DID5</span><br><span style="color: hsl(120, 100%, 40%);">+ NXD6, 32, // 0xdc - IGD _DGS next DID6</span><br><span style="color: hsl(120, 100%, 40%);">+ NXD7, 32, // 0xe0 - IGD _DGS next DID7</span><br><span style="color: hsl(120, 100%, 40%);">+ NXD8, 32, // 0xe4 - IGD _DGS next DID8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI)</span><br><span style="color: hsl(120, 100%, 40%);">+ PAVP, 8, // 0xe9 - IGD PAVP data</span><br><span style="color: hsl(120, 100%, 40%);">+ Offset (0xeb),</span><br><span style="color: hsl(120, 100%, 40%);">+ OSCC, 8, // 0xeb - PCIe OSC control</span><br><span style="color: hsl(120, 100%, 40%);">+ NPCE, 8, // 0xec - native pcie support</span><br><span style="color: hsl(120, 100%, 40%);">+ PLFL, 8, // 0xed - platform flavor</span><br><span style="color: hsl(120, 100%, 40%);">+ BREV, 8, // 0xee - board revision</span><br><span style="color: hsl(120, 100%, 40%);">+ DPBM, 8, // 0xef - digital port b mode</span><br><span style="color: hsl(120, 100%, 40%);">+ DPCM, 8, // 0xf0 - digital port c mode</span><br><span style="color: hsl(120, 100%, 40%);">+ DPDM, 8, // 0xf1 - digital port d mode</span><br><span style="color: hsl(120, 100%, 40%);">+ ALFP, 8, // 0xf2 - active lfp</span><br><span style="color: hsl(120, 100%, 40%);">+ IMON, 8, // 0xf3 - current graphics turbo imon value</span><br><span style="color: hsl(120, 100%, 40%);">+ MMIO, 8, // 0xf4 - 64bit mmio support</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* ChromeOS specific */</span><br><span> Offset (0x100),</span><br><span> #include <vendorcode/google/chromeos/acpi/gnvs.asl></span><br><span>diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c</span><br><span>index 4328abb..8481446 100644</span><br><span>--- a/src/soc/intel/braswell/gfx.c</span><br><span>+++ b/src/soc/intel/braswell/gfx.c</span><br><span>@@ -20,8 +20,10 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/gma/opregion.h></span><br><span> #include <reg_script.h></span><br><span> #include <soc/gfx.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/nvs.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/ramstage.h></span><br><span> </span><br><span>@@ -73,6 +75,21 @@</span><br><span> </span><br><span> /* Post VBIOS Init */</span><br><span> gfx_post_vbios_init(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ intel_gma_restore_opregion();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t gma_get_gnvs_aslb(const void *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const global_nvs_t *gnvs_ptr = gnvs;</span><br><span style="color: hsl(120, 100%, 40%);">+ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ global_nvs_t *gnvs_ptr = gnvs;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gnvs_ptr)</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs_ptr->aslb = aslb;</span><br><span> }</span><br><span> </span><br><span> static struct device_operations gfx_device_ops = {</span><br><span>diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h</span><br><span>index 9b921c5..89a434b 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/nvs.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/nvs.h</span><br><span>@@ -63,7 +63,42 @@</span><br><span> u32 cmem; /* 0x30 - CBMEM TOC */</span><br><span> u32 tolm; /* 0x34 - Top of Low Memory */</span><br><span> u32 cbmc; /* 0x38 - coreboot memconsole */</span><br><span style="color: hsl(0, 100%, 40%);">- u8 rsvd3[196];</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IGD OpRegion */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ibtt; /* 0xb8 - IGD boot type */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ipat; /* 0xb9 - IGD panel type */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 itvf; /* 0xba - IGD TV format */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 itvm; /* 0xbb - IGD TV minor format */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ipsc; /* 0xbc - IGD Panel Scaling */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 iblc; /* 0xbd - IGD BLC configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ibia; /* 0xbe - IGD BIA configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 issc; /* 0xbf - IGD SSC configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 i409; /* 0xc0 - IGD 0409 modified settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 i509; /* 0xc1 - IGD 0509 modified settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 i609; /* 0xc2 - IGD 0609 modified settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 i709; /* 0xc3 - IGD 0709 modified settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 idmm; /* 0xc4 - IGD Power Conservation */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 idms; /* 0xc5 - IGD DVMT memory size */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 if1e; /* 0xc6 - IGD Function 1 Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 hvco; /* 0xc7 - IGD HPLL VCO */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 pavp; /* 0xe9 - IGD PAVP data */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 rsvd12; /* 0xea - rsvd */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 oscc; /* 0xeb - PCIe OSC control */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 npce; /* 0xec - native pcie support */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 plfl; /* 0xed - platform flavor */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 brev; /* 0xee - board revision */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dpbm; /* 0xef - digital port b mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dpcm; /* 0xf0 - digital port c mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 dpdm; /* 0xf1 - digital port c mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 alfp; /* 0xf2 - active lfp */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 imon; /* 0xf3 - current graphics turbo imon value */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 mmio; /* 0xf4 - 64bit mmio support */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 unused[11];</span><br><span> </span><br><span> /* ChromeOS specific (0x100-0xfff) */</span><br><span> chromeos_acpi_t chromeos;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25197">change 25197</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25197"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508 </div>
<div style="display:none"> Gerrit-Change-Number: 25197 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>