<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25187">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Add config option for enabling hotplug<br><br>PcieRpHotPlug in apollolake UPD is default enabled. This change adds a<br>config option to enable hotplug only if explicitly requested by<br>mainboard. This changes the default behavior on all apollolake boards<br>to have hotplug disabled.<br><br>BUG=b:74633273<br><br>Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d<br>Signed-off-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/soc/intel/apollolake/chip.c<br>M src/soc/intel/apollolake/chip.h<br>2 files changed, 6 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/25187/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index 6006773..af145c0 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -534,6 +534,9 @@</span><br><span>     memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin,</span><br><span>                sizeof(silconfig->PcieRpClkReqNumber));</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+          sizeof(silconfig->PcieRpHotPlug));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>       if (cfg->emmc_tx_cmd_cntl != 0)</span><br><span>           silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;</span><br><span>      if (cfg->emmc_tx_data_cntl1 != 0)</span><br><span>diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h</span><br><span>index 7a1d16a..fe845ab 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.h</span><br><span>+++ b/src/soc/intel/apollolake/chip.h</span><br><span>@@ -46,6 +46,9 @@</span><br><span>     */</span><br><span>  uint8_t pcie_rp_clkreq_pin[MAX_PCIE_PORTS];</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+       /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable). */</span><br><span style="color: hsl(120, 100%, 40%);">+       uint8_t pcie_rp_hotplug_enable[MAX_PCIE_PORTS];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>    /* [14:8] DDR mode Number of dealy elements.Each = 125pSec.</span><br><span>   * [6:0] SDR mode Number of dealy elements.Each = 125pSec.</span><br><span>    */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25187">change 25187</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25187"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d </div>
<div style="display:none"> Gerrit-Change-Number: 25187 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>