<p>V Sowmya has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25194">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel/kblrvp8:[WIP] Add KBLRVP8 support<br><br>Add the config for setting SPD DIMM size to 512 bytes<br>for KBLRVP8 with DDR4 memory. Configure the channel 1<br>DIMM0 and DIMM1 memory SPD data. Set the UserBd UPD to<br>BOARD_TYPE_DESKTOP.<br><br>Signed-off-by: V Sowmya <v.sowmya@intel.com><br>Change-Id: I985968d331991884050c3920ec9798cd4cb371c7<br>---<br>M src/mainboard/intel/kblrvp/Kconfig<br>M src/mainboard/intel/kblrvp/romstage.c<br>2 files changed, 12 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/25194/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig</span><br><span>index 5ca46e1..bbeb129 100644</span><br><span>--- a/src/mainboard/intel/kblrvp/Kconfig</span><br><span>+++ b/src/mainboard/intel/kblrvp/Kconfig</span><br><span>@@ -98,4 +98,7 @@</span><br><span>         hex</span><br><span>  default 0xd00</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config DIMM_SPD_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+       int</span><br><span style="color: hsl(120, 100%, 40%);">+   default 512 if BOARD_INTEL_KBLRVP8 #DDR4</span><br><span> endif</span><br><span>diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c</span><br><span>index 7bfbe1c..558c0be 100644</span><br><span>--- a/src/mainboard/intel/kblrvp/romstage.c</span><br><span>+++ b/src/mainboard/intel/kblrvp/romstage.c</span><br><span>@@ -49,7 +49,7 @@</span><br><span>               mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);</span><br><span>              /* Memory leak is ok since we have memory mapped boot media */</span><br><span>               mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);</span><br><span style="color: hsl(0, 100%, 40%);">-  } else {  /* for CONFIG_BOARD_INTEL_KBLRVP7 */</span><br><span style="color: hsl(120, 100%, 40%);">+        } else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8*/</span><br><span>              struct spd_block blk = {</span><br><span>                     .addr_map = { 0x50, 0x51, 0x52, 0x53, },</span><br><span>             };</span><br><span>@@ -58,8 +58,14 @@</span><br><span>              get_spd_smbus(&blk);</span><br><span>             mem_cfg->MemorySpdDataLen = blk.len;</span><br><span>              mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0];</span><br><span style="color: hsl(0, 100%, 40%);">-     }</span><br><span style="color: hsl(0, 100%, 40%);">-       mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;</span><br><span style="color: hsl(120, 100%, 40%);">+              mem_cfg->MemorySpdPtr01 = (u32)blk.spd_array[1];</span><br><span style="color: hsl(120, 100%, 40%);">+           if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) {</span><br><span style="color: hsl(120, 100%, 40%);">+                 mem_cfg->MemorySpdPtr10 = (u32)blk.spd_array[2];</span><br><span style="color: hsl(120, 100%, 40%);">+                   mem_cfg->MemorySpdPtr11 = (u32)blk.spd_array[3];</span><br><span style="color: hsl(120, 100%, 40%);">+           }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span>    mupd->FspmTestConfig.DmiVc1 = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+   if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))</span><br><span style="color: hsl(120, 100%, 40%);">+           mem_cfg->UserBd = BOARD_TYPE_DESKTOP;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25194">change 25194</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25194"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 </div>
<div style="display:none"> Gerrit-Change-Number: 25194 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: V Sowmya <v.sowmya@intel.com> </div>