<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25116">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add SaGv value definition<br><br>SaGv(Sytem Agent Dynamic Frequency) have four settings, disabled,<br>disabled but running at fixed lower frequency, disabled but running at<br>fixed middle frquency, disabled but running at fixed high frequency and<br>totally enabled.<br><br>BUG=None.<br><br>Change-Id: Ib5fb648179e7889aaa64d91e6cf7a7a7503f4225<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/chip.h<br>1 file changed, 8 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/25116/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h</span><br><span>index 5e70fae..241f55e 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.h</span><br><span>+++ b/src/soc/intel/cannonlake/chip.h</span><br><span>@@ -107,6 +107,14 @@</span><br><span>   * When enabled memory will be training at two different frequencies.</span><br><span>         * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */</span><br><span>     uint8_t SaGv;</span><br><span style="color: hsl(120, 100%, 40%);">+ enum {</span><br><span style="color: hsl(120, 100%, 40%);">+                SaGv_Disabled,</span><br><span style="color: hsl(120, 100%, 40%);">+                SaGv_FixedLow,</span><br><span style="color: hsl(120, 100%, 40%);">+                SaGv_FixedMid,</span><br><span style="color: hsl(120, 100%, 40%);">+                SaGv_FixedHigh,</span><br><span style="color: hsl(120, 100%, 40%);">+               SaGv_Enabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ } MrcSaGv;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> </span><br><span>     /* Rank Margin Tool. 1:Enable, 0:Disable */</span><br><span>  uint8_t RMT;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25116">change 25116</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25116"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib5fb648179e7889aaa64d91e6cf7a7a7503f4225 </div>
<div style="display:none"> Gerrit-Change-Number: 25116 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>