<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25020">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[UNTESTED] soc/intel/braswell/lpe: Remove ASL remnants of BAR1<br><br>LPB1 in NVS is never set by coreboot. Drop this copy-pasta and see if<br>it's less confusing for the OS.<br><br>Change-Id: Ic265afc2b27c261ebdde42337c9dcc7c1ccc84f3<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/soc/intel/braswell/acpi/device_nvs.asl<br>M src/soc/intel/braswell/acpi/lpe.asl<br>M src/soc/intel/braswell/include/soc/device_nvs.h<br>M src/soc/intel/braswell/lpe.c<br>4 files changed, 3 insertions(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/25020/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl</span><br><span>index 0d4bc3c..d67e71f 100644</span><br><span>--- a/src/soc/intel/braswell/acpi/device_nvs.asl</span><br><span>+++ b/src/soc/intel/braswell/acpi/device_nvs.asl</span><br><span>@@ -75,7 +75,7 @@</span><br><span> C0B1, 32, /* MMC BAR1 */</span><br><span> C1B1, 32, /* SDIO BAR1 */</span><br><span> C2B1, 32, /* SD Card BAR1 */</span><br><span style="color: hsl(0, 100%, 40%);">-LPB1, 32, /* LPE BAR1 */</span><br><span style="color: hsl(120, 100%, 40%);">+RSV1, 32, /* reserved */</span><br><span> </span><br><span> /* Extra */</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl</span><br><span>index 145e608..c1369b0 100644</span><br><span>--- a/src/soc/intel/braswell/acpi/lpe.asl</span><br><span>+++ b/src/soc/intel/braswell/acpi/lpe.asl</span><br><span>@@ -20,12 +20,10 @@</span><br><span> Name (_CID, "808622A8")</span><br><span> Name (_UID, 1)</span><br><span> Name (_DDN, "Intel(R) Low Power Audio Controller - 808622A8")</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_PR0, Package () { PLPE })</span><br><span> </span><br><span> Name (RBUF, ResourceTemplate()</span><br><span> {</span><br><span> Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0)</span><br><span style="color: hsl(0, 100%, 40%);">- Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1)</span><br><span> Memory32Fixed (ReadWrite, 0, 0x00200000, BAR2)</span><br><span> Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)</span><br><span> {</span><br><span>@@ -59,10 +57,6 @@</span><br><span> CreateDwordField (^RBUF, ^BAR0._BAS, BAS0)</span><br><span> Store (\LPB0, BAS0)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Update BAR1 from NVS */</span><br><span style="color: hsl(0, 100%, 40%);">- CreateDwordField (^RBUF, ^BAR1._BAS, BAS1)</span><br><span style="color: hsl(0, 100%, 40%);">- Store (\LPB1, BAS1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Update LPE FW from NVS */</span><br><span> CreateDwordField (^RBUF, ^BAR2._BAS, BAS2)</span><br><span> Store (\LPFW, BAS2)</span><br><span>@@ -84,31 +78,4 @@</span><br><span> Return (0x0)</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- OperationRegion (KEYS, SystemMemory, LPB1, 0x100)</span><br><span style="color: hsl(0, 100%, 40%);">- Field (KEYS, DWordAcc, NoLock, WriteAsZeros)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Offset (0x84),</span><br><span style="color: hsl(0, 100%, 40%);">- PSAT, 32,</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- PowerResource (PLPE, 0, 0)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Method (_STA)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (1)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Method (_OFF)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Or (PSAT, 0x00000003, PSAT)</span><br><span style="color: hsl(0, 100%, 40%);">- Or (PSAT, 0x00000000, PSAT)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Method (_ON)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- And (PSAT, 0xfffffffc, PSAT)</span><br><span style="color: hsl(0, 100%, 40%);">- Or (PSAT, 0x00000000, PSAT)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span> }</span><br><span>diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h</span><br><span>index 268655e..a97ac54 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/device_nvs.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/device_nvs.h</span><br><span>@@ -56,7 +56,7 @@</span><br><span> /* BAR 0 */</span><br><span> u32 lpss_bar1[14];</span><br><span> u32 scc_bar1[3];</span><br><span style="color: hsl(0, 100%, 40%);">- u32 lpe_bar1;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reserved1;</span><br><span> </span><br><span> /* Extra */</span><br><span> u32 lpe_fw; /* LPE Firmware */</span><br><span>diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c</span><br><span>index 8ec944b..b65c158 100644</span><br><span>--- a/src/soc/intel/braswell/lpe.c</span><br><span>+++ b/src/soc/intel/braswell/lpe.c</span><br><span>@@ -75,10 +75,8 @@</span><br><span> return;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Save BAR0, BAR1, and firmware base to ACPI NVS */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Save BAR0 and firmware base to ACPI NVS */</span><br><span> assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);</span><br><span style="color: hsl(0, 100%, 40%);">- /* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); */</span><br><span> assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);</span><br><span> </span><br><span> /* Device is enabled in ACPI mode */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25020">change 25020</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25020"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic265afc2b27c261ebdde42337c9dcc7c1ccc84f3 </div>
<div style="display:none"> Gerrit-Change-Number: 25020 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>