<p>Garrett Kirkendall has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25025">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Function to Enable ACPI MMIO<br><br>* Add definitions for needed registers in southbridge.h<br>* Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to<br>  0xfed81ffff.  Will be called by a later commit.<br><br>BUG=b:65442212<br>BRANCH=master<br>TEST=abuild, build Gardenia, build boot Grunt<br><br>Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26<br>Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 15 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25025/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index acdaa8a..88403e6 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -32,6 +32,8 @@</span><br><span> #define  PSP_MAILBOX_BAR_EN                0x10</span><br><span> </span><br><span> /* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM_ISA_CONTROL                 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define   MMIO_EN                 BIT(1)</span><br><span> #define PM_PCI_CTRL                   0x08</span><br><span> #define   FORCE_SLPSTATE_RETRY          BIT(25)</span><br><span> #define   FORCE_STPCLK_RETRY         BIT(24)</span><br><span>@@ -349,6 +351,7 @@</span><br><span> void southbridge_init(void *chip_info);</span><br><span> void sb_lpc_port80(void);</span><br><span> void sb_lpc_decode(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_acpi_mmio_decode(void);</span><br><span> void sb_pci_port80(void);</span><br><span> void sb_read_mode(u32 mode);</span><br><span> void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 57bd3f0..c591c69 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -367,6 +367,18 @@</span><br><span>        pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void sb_acpi_mmio_decode(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+  uint8_t byte;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+       /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */</span><br><span style="color: hsl(120, 100%, 40%);">+  outb(PM_ISA_CONTROL, PM_INDEX);</span><br><span style="color: hsl(120, 100%, 40%);">+       byte = inb(PM_DATA);</span><br><span style="color: hsl(120, 100%, 40%);">+  byte |= MMIO_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+      outb(PM_ISA_CONTROL, PM_INDEX);</span><br><span style="color: hsl(120, 100%, 40%);">+       outb(byte, PM_DATA);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void sb_clk_output_48Mhz(void)</span><br><span> {</span><br><span>     u32 ctrl;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25025">change 25025</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25025"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26 </div>
<div style="display:none"> Gerrit-Change-Number: 25025 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> </div>