<p>Garrett Kirkendall has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25010">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/amd/stoneyridge: clean up southbridge.c<br><br>* Limit dependency on vendorcode header files and use defines from<br> iomap.h and southbridge.h<br>* Factor out to functions, device power-on code for AMBA and UART.<br><br>BUG=b:69220826<br>BRANCH=master<br>TEST=abuild, build Gardenia, build and boot Grunt<br><br>Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea<br>Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com><br>---<br>M src/soc/amd/stoneyridge/southbridge.c<br>1 file changed, 38 insertions(+), 25 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/25010/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index c1dd516..598150f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -30,7 +30,6 @@</span><br><span> #include <fchec.h></span><br><span> #include <delay.h></span><br><span> #include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <agesa_headers.h></span><br><span> </span><br><span> static int is_sata_config(void)</span><br><span> {</span><br><span>@@ -272,42 +271,56 @@</span><br><span> return index;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void configure_stoneyridge_uart(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static void power_on_aoac_device(int aoac_device_control_register)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u8 byte, byte2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t byte;</span><br><span> </span><br><span> /* Power on the UART and AMBA devices */</span><br><span style="color: hsl(0, 100%, 40%);">- byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56</span><br><span style="color: hsl(0, 100%, 40%);">- + CONFIG_UART_FOR_CONSOLE * 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = read8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ + aoac_device_control_register);</span><br><span> byte |= AOAC_PWR_ON_DEV;</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56</span><br><span style="color: hsl(0, 100%, 40%);">- + CONFIG_UART_FOR_CONSOLE * 2, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ + aoac_device_control_register, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62);</span><br><span style="color: hsl(0, 100%, 40%);">- byte |= AOAC_PWR_ON_DEV;</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+static bool is_aoac_device_enabled(int aoac_device_status_register)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t byte;</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = read8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ + aoac_device_status_register);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE))</span><br><span style="color: hsl(120, 100%, 40%);">+ return true;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return false;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void configure_stoneyridge_uart(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ bool status;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Power on the UART and AMBA devices */</span><br><span style="color: hsl(120, 100%, 40%);">+ power_on_aoac_device(AOAC_D3_CONTROL_UART0</span><br><span style="color: hsl(120, 100%, 40%);">+ + CONFIG_UART_FOR_CONSOLE * 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ power_on_aoac_device(AOAC_D3_CONTROL_AMBA);</span><br><span> </span><br><span> /* Set the GPIO mux to UART */</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((uint8_t *)(uintptr_t)IOMUX_MMIO_BASE + UART0_RTS_L_EGPIO137,</span><br><span style="color: hsl(120, 100%, 40%);">+ UART0_RTS_L);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((uint8_t *)(uintptr_t)IOMUX_MMIO_BASE + UART0_TXD_EGPIO138,</span><br><span style="color: hsl(120, 100%, 40%);">+ UART0_TXD);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((uint8_t *)(uintptr_t)IOMUX_MMIO_BASE + UART1_RTS_L_EGPIO142,</span><br><span style="color: hsl(120, 100%, 40%);">+ UART1_RTS_L);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((uint8_t *)(uintptr_t)IOMUX_MMIO_BASE + UART1_TXD_EGPIO143,</span><br><span style="color: hsl(120, 100%, 40%);">+ UART1_TXD);</span><br><span> </span><br><span> /* Wait for the UART and AMBA devices to indicate power and clock OK */</span><br><span> do {</span><br><span> udelay(100);</span><br><span style="color: hsl(0, 100%, 40%);">- byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG57</span><br><span style="color: hsl(120, 100%, 40%);">+ status = is_aoac_device_enabled(AOAC_D3_STATE_UART0</span><br><span> + CONFIG_UART_FOR_CONSOLE * 2);</span><br><span style="color: hsl(0, 100%, 40%);">- byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);</span><br><span style="color: hsl(0, 100%, 40%);">- byte2 = read8((void *)ACPI_MMIO_BASE + AOAC_BASE</span><br><span style="color: hsl(0, 100%, 40%);">- + FCH_AOAC_REG63);</span><br><span style="color: hsl(0, 100%, 40%);">- byte2 &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);</span><br><span style="color: hsl(0, 100%, 40%);">- } while (!((byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)) &&</span><br><span style="color: hsl(0, 100%, 40%);">- (byte2 == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE))));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ status &= is_aoac_device_enabled(AOAC_D3_STATE_AMBA);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while (!status);</span><br><span> }</span><br><span> </span><br><span> void sb_pci_port80(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25010">change 25010</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea </div>
<div style="display:none"> Gerrit-Change-Number: 25010 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> </div>