<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25015">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/kahlee: Disable Bayhub part on board_id 0<br><br>The Bayhub part is not used on proto with board_id 0, so disable it.<br><br>BUG=b:74248569<br>TEST=Build & boot Grunt. Bayhub part is disabled.<br><br>Change-Id: I635356d41bab637726594d403d66dde730f12256<br>Signed-off-by: Martin Roth <martinroth@chromium.org><br>---<br>M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c<br>1 file changed, 99 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/25015/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c</span><br><span>index aa0edf7..c9ce900 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <amdblocks/agesawrapper.h></span><br><span> #include <variant/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <boardid.h></span><br><span> </span><br><span> static const PCIe_PORT_DESCRIPTOR PortList[] = {</span><br><span> /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/</span><br><span>@@ -127,6 +128,98 @@</span><br><span> .DdiLinkList = (void *)DdiList</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * TODO: Remove after we're done with Grunt Proto</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+static const PCIe_PORT_DESCRIPTOR PortListNoBayhub[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(120, 100%, 40%);">+ PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(120, 100%, 40%);">+ ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ 1, /* mDevFunction */</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, /* mResetId */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) /* mClkPmSupport */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lanes 0:0, D2F2) for WLAN */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(120, 100%, 40%);">+ PortEnabled, /* mPortPresent */</span><br><span style="color: hsl(120, 100%, 40%);">+ ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevFunction */</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_0_RST, /* mResetId */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) /* mClkPmSupport */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Init Port descriptor (PCIe port, Lanes 1:1, D2F3) NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(120, 100%, 40%);">+ PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(120, 100%, 40%);">+ ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ 3, /* mDevFunction */</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_1_RST, /* mResetId */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) /* mClkPmSupport */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for EMMC */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 2, 2),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(120, 100%, 40%);">+ PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(120, 100%, 40%);">+ ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ 4, /* mDevFunction */</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_2_RST, /* mResetId */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) /* mClkPmSupport */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for NC */</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 3, 3),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER_V2(</span><br><span style="color: hsl(120, 100%, 40%);">+ PortDisabled, /* mPortPresent */</span><br><span style="color: hsl(120, 100%, 40%);">+ ChannelTypeExt6db, /* mChannelType */</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, /* mDevAddress */</span><br><span style="color: hsl(120, 100%, 40%);">+ 5, /* mDevFunction */</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, /* mHotplug */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkSpeed */</span><br><span style="color: hsl(120, 100%, 40%);">+ PcieGenMaxSupported, /* mMaxLinkCap */</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, /* mAspm */</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_3_RST, /* mResetId */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) /* mClkPmSupport */</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+static const PCIe_COMPLEX_DESCRIPTOR PcieNoBayhub = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .Flags = DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .SocketId = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .PciePortList = (void *)PortListNoBayhub,</span><br><span style="color: hsl(120, 100%, 40%);">+ .DdiLinkList = (void *)DdiList</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*---------------------------------------------------------------------------*/</span><br><span> /**</span><br><span> * OemCustomizeInitEarly</span><br><span>@@ -148,4 +241,10 @@</span><br><span> InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;</span><br><span> InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;</span><br><span> InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Completely disable Bayhub EMMC bridge on Proto with board_id 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Todo: Remove when we're done with Proto */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (board_id() == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ InitEarly->GnbConfig.PcieComplexList = (void *)&PcieNoBayhub;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25015">change 25015</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25015"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I635356d41bab637726594d403d66dde730f12256 </div>
<div style="display:none"> Gerrit-Change-Number: 25015 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>