<p>Garrett Kirkendall has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25009">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/amd/stoneyridge: clean up OSCOUT1_ClkOutputEnb<br><br>Change OSCOUT1_ClkOutputEnb programming to use registers from iomap.h<br>and southbridge.h<br><br>BUG=b:69220826<br>BRANCH=master<br>TEST=abuild, build Gardenia, build and boot Grunt<br><br>Change-Id: Ib138dae6057394740c415e882e4dbd925882c2de<br>Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 7 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/25009/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 7eba4d6..599fa68 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -247,7 +247,8 @@</span><br><span> #define SPI100_HOST_PREF_CONFIG              0x2c</span><br><span> #define   SPI_RD4DW_EN_HOST             BIT(15)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_MISC_REG40_OSCOUT1_EN    BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_MISC_CLK_CNTL_1            0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define   OSCOUT1_CLK_OUTPUT_ENB  BIT(2)  // 0 = Enabled, 1 = Disabled</span><br><span> </span><br><span> /* IO 0xcf9 - Reset control port*/</span><br><span> #define   FULL_RST                    BIT(3)</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 3d0cc74..c1dd516 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -365,11 +365,13 @@</span><br><span>       * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so</span><br><span>      * 48Mhz will be on ball AP13 (FT3b package)</span><br><span>          */</span><br><span style="color: hsl(0, 100%, 40%);">-     ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40));</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl = read32((u32 *)(uintptr_t)(MISC_MMIO_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+                               + MISC_MISC_CLK_CNTL_1));</span><br><span> </span><br><span>        /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl &= ~FCH_MISC_REG40_OSCOUT1_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;</span><br><span style="color: hsl(120, 100%, 40%);">+  write32((u32 *)(uintptr_t)(MISC_MMIO_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+                             + MISC_MISC_CLK_CNTL_1), ctrl);</span><br><span> }</span><br><span> </span><br><span> static uintptr_t sb_spibase(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25009">change 25009</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25009"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib138dae6057394740c415e882e4dbd925882c2de </div>
<div style="display:none"> Gerrit-Change-Number: 25009 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> </div>