<p>Robert Reeves has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25008">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/hp: Add HP Elitebook 8770w (take 2)<br><br>This is based on the code from the 8470p port. Tested on the quad<br>core/quad SODIMM version. This laptop uses discrete MXM 3.0b graphics<br>cards. Tested working with both Quadro K3000M and GTX 980M 8GB. The<br>laptop must be completely disassembled down to the motherboard to<br>perform the initial flash, subsequent flashes can be done internally<br>via flashrom. There is a simple mod that can be performed to make<br>subsequent external flashes easier in case of a brick, I'll put more<br>information on this on the wiki later. The lack of an MXM structure<br>built in to the firmware causes the GPU to enter a mode with nerfed<br>performance, there is a workaround though, I'll add this to the wiki<br>as well. I have no info on EHCI debugging.<br><br>Tested and working:<br>- memory: 4G+4G, 4G+4G+4G+4G<br>- Linux (Debian Stretch with kernel 4.9.0) booted from SeaBIOS payload<br>with graphics init disabled in coreboot. I allowed SeaBIOS to load the<br>VBIOS from the MXM.<br>- WLAN<br>- keyboard, trackpoint and touchpad<br>- USB2.0 & 3.0<br>- serial port on dock<br>- fan control<br>- VGA<br>- DisplayPort<br>- Audio<br>- Both HDD SATA ports, ODD SATA, eSATA<br>- S3 with SeaBIOS 1.11, SERCON must be disabled<br>- Brightness and volume FN keys<br>- Mute and calculator hardware buttons<br>- Status LEDs<br><br>Not working:<br>- Bluetooth, I believe this has to do with GPIO72, I'll figure it out<br>later.<br>- Sleep FN key<br>- Wifi toggle and internet browser hardware buttons<br><br>Change-Id: I3c4de6533e155f98cf0505cbc169e39f68855dca<br>Signed-off-by: Robert Reeves <xiinc37@gmail.com><br>---<br>A src/mainboard/hp/8770w/Kconfig<br>A src/mainboard/hp/8770w/Kconfig.name<br>A src/mainboard/hp/8770w/Makefile.inc<br>A src/mainboard/hp/8770w/acpi/ec.asl<br>A src/mainboard/hp/8770w/acpi/platform.asl<br>A src/mainboard/hp/8770w/acpi/superio.asl<br>A src/mainboard/hp/8770w/acpi_tables.c<br>A src/mainboard/hp/8770w/board_info.txt<br>A src/mainboard/hp/8770w/cmos.default<br>A src/mainboard/hp/8770w/cmos.layout<br>A src/mainboard/hp/8770w/devicetree.cb<br>A src/mainboard/hp/8770w/dsdt.asl<br>A src/mainboard/hp/8770w/gpio.c<br>A src/mainboard/hp/8770w/hda_verb.c<br>A src/mainboard/hp/8770w/mainboard.c<br>A src/mainboard/hp/8770w/romstage.c<br>16 files changed, 889 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/25008/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..c650309</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/Kconfig</span><br><span>@@ -0,0 +1,68 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2018 Robert Reeves</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_HP_8770W</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_SOCKET_RPGA989</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_INT15</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_IVYBRIDGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SERIRQ_CONTINUOUS_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_C216</span><br><span style="color: hsl(120, 100%, 40%);">+ select SYSTEM_TYPE_LAPTOP</span><br><span style="color: hsl(120, 100%, 40%);">+ select USE_NATIVE_RAMINIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select EC_HP_KBC1126</span><br><span style="color: hsl(120, 100%, 40%);">+ select SUPERIO_SMSC_LPC47N217</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HAVE_IFD_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HAVE_ME_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default hp/8770w</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "EliteBook 8770w"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x103c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config USBDEBUG_HCD_INDEX</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/hp/8770w/Kconfig.name b/src/mainboard/hp/8770w/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..df9981c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_HP_8770W</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "EliteBook 8770w"</span><br><span>diff --git a/src/mainboard/hp/8770w/Makefile.inc b/src/mainboard/hp/8770w/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..d57c9b5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/Makefile.inc</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span>diff --git a/src/mainboard/hp/8770w/acpi/ec.asl b/src/mainboard/hp/8770w/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..ac65fb3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/acpi/ec.asl</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/hp/kbc1126/acpi/ec.asl></span><br><span>diff --git a/src/mainboard/hp/8770w/acpi/platform.asl b/src/mainboard/hp/8770w/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..fe0f936</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/acpi/platform.asl</span><br><span>@@ -0,0 +1,27 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_WAK,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.LPCB.EC0.ACPI = 1</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.LPCB.EC0.SLPT = 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(Package(){0,0})</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PTS,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.LPCB.EC0.SLPT = Arg0</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/hp/8770w/acpi/superio.asl b/src/mainboard/hp/8770w/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..b3ea115</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/acpi/superio.asl</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/pc80/pc/ps2_controller.asl></span><br><span>diff --git a/src/mainboard/hp/8770w/acpi_tables.c b/src/mainboard/hp/8770w/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d8d89e4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/acpi_tables.c</span><br><span>@@ -0,0 +1,33 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S3 by default */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S5 by default */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // the lid is open by default.</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->lids = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tcrt = 100;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tpsv = 90;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/hp/8770w/board_info.txt b/src/mainboard/hp/8770w/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..0d04ad0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/board_info.txt</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: laptop</span><br><span style="color: hsl(120, 100%, 40%);">+Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8770w-Mobile-Workstation/5257511</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOIC-16</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: n</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2012</span><br><span>diff --git a/src/mainboard/hp/8770w/cmos.default b/src/mainboard/hp/8770w/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..fcbe0fb</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/cmos.default</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Spew</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+volume=0x3</span><br><span style="color: hsl(120, 100%, 40%);">+sata_mode=AHCI</span><br><span>diff --git a/src/mainboard/hp/8770w/cmos.layout b/src/mainboard/hp/8770w/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..7b95f69</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/cmos.layout</span><br><span>@@ -0,0 +1,109 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2018 Robert Reeves</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#390 2 r 0 unused?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#400 8 r 0 reserved for century byte</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+421 1 e 9 sata_mode</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: cpu</span><br><span style="color: hsl(120, 100%, 40%);">+#424 8 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+#435 5 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+440 8 h 0 volume</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# SandyBridge MRC Scrambler Seed values</span><br><span style="color: hsl(120, 100%, 40%);">+896 32 r 0 mrc_scrambler_seed</span><br><span style="color: hsl(120, 100%, 40%);">+928 32 r 0 mrc_scrambler_seed_s3</span><br><span style="color: hsl(120, 100%, 40%);">+960 16 r 0 mrc_scrambler_seed_chk</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+9 0 AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+9 1 Compatible</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 447 984</span><br><span>diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..867bc02</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/devicetree.cb</span><br><span>@@ -0,0 +1,146 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+# Copyright (C) 2018 Robert Reeves</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+# it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+# the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+# (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+# This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+# but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+# GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+#</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/sandybridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_rPGA989</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_206ax</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_acpower" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_battery" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_acpower" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_battery" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_acpower" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_battery" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xacac off</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # Host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 on # PCIe Bridge for discrete graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 off # Internal graphics VGA controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "0x0065"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "docking_supported" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x007c0201"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c0101"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen3_dec" = "0x00fcfe01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen4_dec" = "0x000402e9"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi6_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "p_cnt_throttling_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_port_coalesce" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_interface_speed_support" = "0x3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x1f"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "superspeed_capable_ports" = "0x0000000f"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "xhci_overcurrent_mapping" = "0x00000c03"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "xhci_switchable_ports" = "0x0000000f"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_uvscc" = "0x2005"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_lvscc" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # USB 3.0 Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 on # Management Engine KT</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on # Intel Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on # USB2 EHCI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on # High Definition Audio Audio controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on # PCIe Port #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on # PCIe Port #2</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on # PCIe Port #3</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on # PCIe Port #4</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on # PCIe Port #5</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off # PCIe Port #6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off # PCIe Port #7</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off # PCIe Port #8</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on # USB2 EHCI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # LPC bridge PCI-LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/hp/kbc1126</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ec_data_port" = "0x62"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ec_cmd_port" = "0x66"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ec_ctrl_reg" = "0x81"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ec_fan_ctrl_value" = "0x81"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.1 off end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # kbc1126</span><br><span style="color: hsl(120, 100%, 40%);">+ chip superio/smsc/lpc47n217</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 4e.3 on # Parallel</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x378</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 7</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 4e.4 on # Com1</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x3f8</span><br><span style="color: hsl(120, 100%, 40%);">+ irq 0x70 = 4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 4e.5 off # Com2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end #chip superio/smsc/lpc47n217</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on # SATA Controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x103c 0x176c</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 off # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off # SATA Controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/hp/8770w/dsdt.asl b/src/mainboard/hp/8770w/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..51934c7</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/dsdt.asl</span><br><span>@@ -0,0 +1,44 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, // DSDT revision: ACPI v3.0</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", // OEM id</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", // OEM table id</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20141018 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // Some generic macros</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/model_206ax/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ /* global NVS and variables. */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/pch.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/hp/8770w/gpio.c b/src/mainboard/hp/8770w/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..ac054d9</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/gpio.c</span><br><span>@@ -0,0 +1,228 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Robert Reeves</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio30 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_RESET_RSMRST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio30 = GPIO_RESET_RSMRST,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio40 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio58 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio59 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio62 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio63 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio74 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio75 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio74 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio74 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set3 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set3_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set3_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set3_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set3_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/hp/8770w/hda_verb.c b/src/mainboard/hp/8770w/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..51869cb</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/hda_verb.c</span><br><span>@@ -0,0 +1,62 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Robert Reeves</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x111d7605, /* Codec Vendor / Device ID: IDT */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x103c176c, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000000b, /* Number of 4 dword sets */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x01: Subsystem ID. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x0, 0x103c176c),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x0a. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x0a, 0x21011030),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x0b. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421101f),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x0c. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x0d. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x0e. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x0f. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x0f, 0x2181102e),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x10. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x11. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x11, 0xd5a30140),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1f. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x20. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[0] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span>diff --git a/src/mainboard/hp/8770w/mainboard.c b/src/mainboard/hp/8770w/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..9e2634f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/mainboard.c</span><br><span>@@ -0,0 +1,26 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Robert Reeves</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..9fa7e8c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/hp/8770w/romstage.c</span><br><span>@@ -0,0 +1,83 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Robert Reeves</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/sandybridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/raminit_native.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <superio/smsc/lpc47n217/lpc47n217.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/hp/kbc1126/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * CNF2 and CNF1 for Super I/O</span><br><span style="color: hsl(120, 100%, 40%);">+ * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable parallel port and serial port</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_LPC_DEV, LPC_EN,</span><br><span style="color: hsl(120, 100%, 40%);">+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |</span><br><span style="color: hsl(120, 100%, 40%);">+ LPT_LPC_EN | COMA_LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 4 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 4 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 5 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 5 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 6 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, 6 },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_early_init(int s3resume)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_config_superio(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);</span><br><span style="color: hsl(120, 100%, 40%);">+ kbc1126_enter_conf();</span><br><span style="color: hsl(120, 100%, 40%);">+ kbc1126_mailbox_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ kbc1126_kbc_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ kbc1126_ec_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ kbc1126_pm1_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ kbc1126_exit_conf();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_get_spd(spd_raw_data *spd, bool id_only)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[0], 0x50, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[1], 0x51, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[2], 0x52, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[3], 0x53, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25008">change 25008</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25008"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3c4de6533e155f98cf0505cbc169e39f68855dca </div>
<div style="display:none"> Gerrit-Change-Number: 25008 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Robert Reeves <xiinc37@gmail.com> </div>