<p>Garrett Kirkendall has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24998">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc/amd/stoneyridge: cleanup southbridge.c<br><br>Limit dependency on vendorcode header files and add appropriate<br>definitions to southbridge.h. Add code to enable decode of FCH ACPI<br>MMIO regions. Factor out to functions, device power-on<br>code for AMBA and UART. Add FCH I2C device power-on code. Add code for<br>FCH to decode TPM memory and IO regions.<br><br>BUG=b:69220826 b:65442212<br>BRANCH=master<br>TEST=Build and boot<br><br>Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac<br>Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>2 files changed, 181 insertions(+), 29 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/24998/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 3489afc..9c75a12 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -31,7 +31,32 @@</span><br><span> #define PSP_BAR_ENABLES 0x48</span><br><span> #define PSP_MAILBOX_BAR_EN 0x10</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* FCH ACPI MMIO register base addresses */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_MMIO_BASE 0xFED80000ul</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_SMBUS_PCI_BASE ACPI_MMIO_BASE + 0x000</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_SMI_BASE ACPI_MMIO_BASE + 0x200</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_PMIO_BASE ACPI_MMIO_BASE + 0x300</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_PMIO2_BASE ACPI_MMIO_BASE + 0x400</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_BIOS_RAM_BASE ACPI_MMIO_BASE + 0x500</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_CMOS_RAM_BASE ACPI_MMIO_BASE + 0x600</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_CMOS_BASE ACPI_MMIO_BASE + 0x700</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_ASF_BASE ACPI_MMIO_BASE + 0x900</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_SMBUS_BASE ACPI_MMIO_BASE + 0xA00</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_WATCHDOG_BASE ACPI_MMIO_BASE + 0xB00</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_HPET_BASE ACPI_MMIO_BASE + 0xC00</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_IOMUX_BASE ACPI_MMIO_BASE + 0xD00</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_MISC_BASE ACPI_MMIO_BASE + 0xE00</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_GFX_DAC_BASE ACPI_MMIO_BASE + 0x1400</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_GPIO_BANK0_BASE ACPI_MMIO_BASE + 0x1500</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_GPIO_BANK1_BASE ACPI_MMIO_BASE + 0x1600</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_GPIO_BANK2_BASE ACPI_MMIO_BASE + 0x1700</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_XHCI_BASE ACPI_MMIO_BASE + 0x1C00</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_ACDC_BASE ACPI_MMIO_BASE + 0x1D00</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_ACPI_MMIO_AOAC_BASE ACPI_MMIO_BASE + 0x1E00</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM_ISA_CONTROL 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define MMIO_EN BIT(1)</span><br><span> #define PM_PCI_CTRL 0x08</span><br><span> #define FORCE_SLPSTATE_RETRY BIT(25)</span><br><span> #define FORCE_STPCLK_RETRY BIT(24)</span><br><span>@@ -161,6 +186,10 @@</span><br><span> #define DECODE_IO_PORT_ENABLE1_H BIT(1)</span><br><span> #define DECODE_IO_PORT_ENABLE0_H BIT(0)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define LPC_TRUSTED_PLATFORM_MODULE 0x7C</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_12_EN BIT(0)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_LEGACY_EN BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * Register 0x64 is 32-bit, composed by two 16-bit sub-registers.</span><br><span> * For ease of access, each sub-register is declared separetely.</span><br><span>@@ -247,7 +276,8 @@</span><br><span> #define SPI100_HOST_PREF_CONFIG 0x2c</span><br><span> #define SPI_RD4DW_EN_HOST BIT(15)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_MISC_REG40_OSCOUT1_EN BIT(2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_MISC_CLK_CNTL_1 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) // 0 = Enabled, 1 = Disabled</span><br><span> </span><br><span> /* IO 0xcf9 - Reset control port*/</span><br><span> #define FULL_RST BIT(3)</span><br><span>@@ -290,6 +320,60 @@</span><br><span> #endif</span><br><span> #define STR_GPIO_STAGE ENV_STRING</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* FCH IOMUX Registers 0xFED80D00 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART0_RTS_L_EGPIO137 0x89</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART0_RTS_L 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define EGPIO_137 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART0_TXD_EGPIO138 0x8A</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART0_TXD 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define EGPIO138 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART1_RTS_L_EGPIO142 0x8E</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART1_RTS_L 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define EGPIO142 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART1_TXD_EGPIO143 0x8F</span><br><span style="color: hsl(120, 100%, 40%);">+#define UART1_TXD 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define EGPIO143 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* FCH AOAC Registers 0xFED81E00 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_CONTROL_CLK_GEN 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_CONTROL_I2C0 0x4A</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_CONTROL_I2C1 0x4C</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_CONTROL_I2C2 0x4E</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_CONTROL_I2C3 0x50</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_CONTROL_UART0 0x56</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_CONTROL_UART1 0x58</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_CONTROL_AMBA 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_CONTROL_USB2 0x64</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_CONTROL_USB3 0x6E</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_TARGET_DEVICE_STATE (BIT0 + BIT1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_DEVICE_STATE BIT2</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_PWR_ON_DEV BIT3</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_SW_PWR_ON_RSTB BIT4</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_SW_REF_CLK_OK BIT5</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_SW_RST_B BIT6</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_IS_SW_CONTROL BIT7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_STATE_CLK_GEN 0x41</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_STATE_I2C0 0x4B</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_STATE_I2C1 0x4D</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_STATE_I2C2 0x4F</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_STATE_I2C3 0x51</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_STATE_UART0 0x57</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_STATE_UART1 0x59</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_STATE_AMBA 0x63</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_STATE_USB2 0x65</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3_STATE_USB3 0x6F</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define A0AC_PWR_RST_STATE BIT0</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_RST_CLK_OK_STATE BIT1</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_RST_B_STATE BIT2</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_DEV_OFF_GATING_STATE BIT3</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_D3COLD BIT4</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_CLK_OK_STATE BIT5</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_STAT0 BIT6</span><br><span style="color: hsl(120, 100%, 40%);">+#define AOAC_STAT1 BIT7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct soc_amd_stoneyridge_gpio {</span><br><span> uint8_t gpio;</span><br><span> uint8_t function;</span><br><span>@@ -298,6 +382,7 @@</span><br><span> </span><br><span> void sb_enable_rom(void);</span><br><span> void configure_stoneyridge_uart(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void configure_stoneyridge_i2c(void);</span><br><span> void sb_clk_output_48Mhz(void);</span><br><span> void sb_disable_4dw_burst(void);</span><br><span> void sb_enable(device_t dev);</span><br><span>@@ -305,10 +390,12 @@</span><br><span> void southbridge_init(void *chip_info);</span><br><span> void sb_lpc_port80(void);</span><br><span> void sb_lpc_decode(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_acpi_mmio_decode(void);</span><br><span> void sb_pci_port80(void);</span><br><span> void sb_read_mode(u32 mode);</span><br><span> void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);</span><br><span> void sb_set_readspeed(u16 norm, u16 fast);</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_tpm_decode(void);</span><br><span> void sb_tpm_decode_spi(void);</span><br><span> void lpc_wideio_512_window(uint16_t base);</span><br><span> void lpc_wideio_16_window(uint16_t base);</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 5d7b73d..82c2ffc 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -30,7 +30,6 @@</span><br><span> #include <fchec.h></span><br><span> #include <delay.h></span><br><span> #include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <agesa_headers.h></span><br><span> </span><br><span> static int is_sata_config(void)</span><br><span> {</span><br><span>@@ -274,42 +273,88 @@</span><br><span> return index;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void configure_stoneyridge_uart(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static void power_on_aoac_device(int aoac_device_control_register)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u8 byte, byte2;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 byte;</span><br><span> </span><br><span> /* Power on the UART and AMBA devices */</span><br><span style="color: hsl(0, 100%, 40%);">- byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56</span><br><span style="color: hsl(0, 100%, 40%);">- + CONFIG_UART_FOR_CONSOLE * 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = read8((void *)FCH_ACPI_MMIO_AOAC_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ + aoac_device_control_register);</span><br><span> byte |= AOAC_PWR_ON_DEV;</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56</span><br><span style="color: hsl(0, 100%, 40%);">- + CONFIG_UART_FOR_CONSOLE * 2, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((void *)FCH_ACPI_MMIO_AOAC_BASE + aoac_device_control_register,</span><br><span style="color: hsl(120, 100%, 40%);">+ byte);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62);</span><br><span style="color: hsl(0, 100%, 40%);">- byte |= AOAC_PWR_ON_DEV;</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+static bool is_aoac_device_enabled(int aoac_device_status_register)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 byte;</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = read8((void *)FCH_ACPI_MMIO_AOAC_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ + aoac_device_status_register);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE))</span><br><span style="color: hsl(120, 100%, 40%);">+ return(true);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ return(false);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void configure_stoneyridge_i2c(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ bool status;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Power on the I2C devices */</span><br><span style="color: hsl(120, 100%, 40%);">+ power_on_aoac_device(AOAC_D3_CONTROL_I2C0);</span><br><span style="color: hsl(120, 100%, 40%);">+ power_on_aoac_device(AOAC_D3_CONTROL_I2C1);</span><br><span style="color: hsl(120, 100%, 40%);">+ power_on_aoac_device(AOAC_D3_CONTROL_I2C2);</span><br><span style="color: hsl(120, 100%, 40%);">+ power_on_aoac_device(AOAC_D3_CONTROL_I2C3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Wait for the I2C devices to indicate power and clock OK */</span><br><span style="color: hsl(120, 100%, 40%);">+ do {</span><br><span style="color: hsl(120, 100%, 40%);">+ udelay(100);</span><br><span style="color: hsl(120, 100%, 40%);">+ status = is_aoac_device_enabled(AOAC_D3_STATE_I2C0);</span><br><span style="color: hsl(120, 100%, 40%);">+ status &= is_aoac_device_enabled(AOAC_D3_STATE_I2C1);</span><br><span style="color: hsl(120, 100%, 40%);">+ status &= is_aoac_device_enabled(AOAC_D3_STATE_I2C2);</span><br><span style="color: hsl(120, 100%, 40%);">+ status &= is_aoac_device_enabled(AOAC_D3_STATE_I2C3);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while (!(status));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void sb_acpi_mmio_decode(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 byte;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable ACPI MMIO range 0xFED80000 - 0xFED81FFF */</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(PM_ISA_CONTROL, PM_INDEX);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = inb(PM_DATA);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte |= MMIO_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(PM_ISA_CONTROL, PM_INDEX);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(byte, PM_DATA);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void configure_stoneyridge_uart(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ bool status;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Power on the UART and AMBA devices */</span><br><span style="color: hsl(120, 100%, 40%);">+ power_on_aoac_device(AOAC_D3_CONTROL_UART0</span><br><span style="color: hsl(120, 100%, 40%);">+ + CONFIG_UART_FOR_CONSOLE * 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ power_on_aoac_device(AOAC_D3_CONTROL_AMBA);</span><br><span> </span><br><span> /* Set the GPIO mux to UART */</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((void *)FCH_ACPI_MMIO_IOMUX_BASE + UART0_RTS_L_EGPIO137,</span><br><span style="color: hsl(120, 100%, 40%);">+ UART0_RTS_L);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((void *)FCH_ACPI_MMIO_IOMUX_BASE + UART0_TXD_EGPIO138,</span><br><span style="color: hsl(120, 100%, 40%);">+ UART0_TXD);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((void *)FCH_ACPI_MMIO_IOMUX_BASE + UART1_RTS_L_EGPIO142,</span><br><span style="color: hsl(120, 100%, 40%);">+ UART1_RTS_L);</span><br><span style="color: hsl(120, 100%, 40%);">+ write8((void *)FCH_ACPI_MMIO_IOMUX_BASE + UART1_TXD_EGPIO143,</span><br><span style="color: hsl(120, 100%, 40%);">+ UART1_TXD);</span><br><span> </span><br><span> /* Wait for the UART and AMBA devices to indicate power and clock OK */</span><br><span> do {</span><br><span> udelay(100);</span><br><span style="color: hsl(0, 100%, 40%);">- byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG57</span><br><span style="color: hsl(120, 100%, 40%);">+ status = is_aoac_device_enabled(AOAC_D3_STATE_UART0</span><br><span> + CONFIG_UART_FOR_CONSOLE * 2);</span><br><span style="color: hsl(0, 100%, 40%);">- byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);</span><br><span style="color: hsl(0, 100%, 40%);">- byte2 = read8((void *)ACPI_MMIO_BASE + AOAC_BASE</span><br><span style="color: hsl(0, 100%, 40%);">- + FCH_AOAC_REG63);</span><br><span style="color: hsl(0, 100%, 40%);">- byte2 &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);</span><br><span style="color: hsl(0, 100%, 40%);">- } while (!((byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)) &&</span><br><span style="color: hsl(0, 100%, 40%);">- (byte2 == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE))));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ status &= is_aoac_device_enabled(AOAC_D3_STATE_AMBA);</span><br><span style="color: hsl(120, 100%, 40%);">+ } while (!(status));</span><br><span> }</span><br><span> </span><br><span> void sb_pci_port80(void)</span><br><span>@@ -367,11 +412,11 @@</span><br><span> * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so</span><br><span> * 48Mhz will be on ball AP13 (FT3b package)</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40));</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl = read32((void *)(FCH_ACPI_MMIO_MISC_BASE + MISC_MISC_CLK_CNTL_1));</span><br><span> </span><br><span> /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */</span><br><span style="color: hsl(0, 100%, 40%);">- ctrl &= ~FCH_MISC_REG40_OSCOUT1_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32((void *)(FCH_ACPI_MMIO_MISC_BASE + MISC_MISC_CLK_CNTL_1), ctrl);</span><br><span> }</span><br><span> </span><br><span> static uintptr_t sb_spibase(void)</span><br><span>@@ -428,8 +473,24 @@</span><br><span> & ~SPI_READ_MODE_MASK) | mode);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void sb_tpm_decode(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable TPM decoding to FCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 value = pci_read_config32(SOC_LPC_DEV,</span><br><span style="color: hsl(120, 100%, 40%);">+ LPC_TRUSTED_PLATFORM_MODULE);</span><br><span style="color: hsl(120, 100%, 40%);">+ value |= (TPM_12_EN | TPM_LEGACY_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void sb_tpm_decode_spi(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable TPM decoding to FCH */</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_tpm_decode();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Make sure SPI base register is programmed */</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_spibase();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Route TPM accesses to SPI */</span><br><span> u32 spibase = pci_read_config32(SOC_LPC_DEV,</span><br><span> SPIROM_BASE_ADDRESS_REGISTER);</span><br><span> pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase</span><br><span>@@ -487,6 +548,10 @@</span><br><span> sb_enable_rom();</span><br><span> sb_lpc_port80();</span><br><span> sb_lpc_decode();</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_set_spi100(SPI_SPEED_33M,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI_SPEED_33M,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI_SPEED_16M,</span><br><span style="color: hsl(120, 100%, 40%);">+ SPI_SPEED_16M);</span><br><span> }</span><br><span> </span><br><span> void sb_enable(device_t dev)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24998">change 24998</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/24998"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac </div>
<div style="display:none"> Gerrit-Change-Number: 24998 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> </div>