<p>Philipp Deppenwiese has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24993">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">security/vboot: Extend measurements for all execution flows<br><br>* Implement blob_hook_region_device for blob<br> measurements.<br>* Move PCR defines for measured boot into<br> secdata_measurements.c<br><br>Change-Id: I3ddfeabd63aefec152a9bc439a415c37b814f94f<br>Signed-off-by: zaolin <zaolin@das-labor.org><br>---<br>M src/security/tpm/tspi.h<br>M src/security/vboot/secdata_measurements.c<br>2 files changed, 81 insertions(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/24993/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h</span><br><span>index 775311e..bf2b7ae 100644</span><br><span>--- a/src/security/tpm/tspi.h</span><br><span>+++ b/src/security/tpm/tspi.h</span><br><span>@@ -21,34 +21,6 @@</span><br><span> </span><br><span> #define TPM_PCR_MAX_LENGTH 64</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-// PCR Registers used by coreboot</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_BOOTBLOCK_PCR 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_STAGE_VERSTAGE_PCR 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_STAGE_ROMSTAGE_PCR 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_STAGE_POSTCAR_PCR 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_STAGE_RAMSTAGE_PCR 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_PAYLOAD_PCR 3</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_FW_MAIN 1</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// Vendor / Platform specific</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_INTEL_FSP_PCR 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_INTEL_FSPM_PCR 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_INTEL_FSPS_PCR 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_INTEL_NHLT_PCR 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_ARM_BL31_PCR 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_ARM_BL32_PCR 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_VGA_OPTION_ROM_PCR 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_SPD_DATA_PCR 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_AMD_PSP_PCR 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_AMD_AGESA_PCR 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_NVIDIA_MTC_PCR 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_VBT_PCR 2</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_MICROCODE_PCR 1</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-// special</span><br><span style="color: hsl(0, 100%, 40%);">-#define TPM_UNKNOWN_PCR 4</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /**</span><br><span> * TPM measurement with acpi log functionality based on binary data.</span><br><span> */</span><br><span>diff --git a/src/security/vboot/secdata_measurements.c b/src/security/vboot/secdata_measurements.c</span><br><span>index 9111ffa..14b5c27 100644</span><br><span>--- a/src/security/vboot/secdata_measurements.c</span><br><span>+++ b/src/security/vboot/secdata_measurements.c</span><br><span>@@ -14,11 +14,30 @@</span><br><span> */</span><br><span> </span><br><span> #include "antirollback.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <blob_provider.h></span><br><span> #include <cbfs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <fmap.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fmap.h></span><br><span> #include <security/tpm/tspi.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+// CRTM</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_BOOTBLOCK_PCR 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_STAGE_VERSTAGE_PCR 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_STAGE_ROMSTAGE_PCR 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Soc Init</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_STAGE_POSTCAR_PCR 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_STAGE_RAMSTAGE_PCR 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_INTEL_FSP_PCR 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Payload</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_PAYLOAD_PCR 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_ARM_BL31_PCR 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_ARM_BL32_PCR 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Unknown</span><br><span style="color: hsl(120, 100%, 40%);">+#define TPM_UNKNOWN_PCR 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> uint32_t vboot_measure_crtm(void)</span><br><span> {</span><br><span> struct prog bootblock = PROG_INIT(PROG_BOOTBLOCK, "bootblock");</span><br><span>@@ -29,19 +48,17 @@</span><br><span> </span><br><span> /* measure bootblock from RO */</span><br><span> struct cbfsf bootblock_data;</span><br><span style="color: hsl(0, 100%, 40%);">- if (!cbfs_boot_locate(&bootblock_data, prog_name(&bootblock), NULL)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cbfs_boot_locate(&bootblock_data, prog_name(&bootblock), NULL) ==</span><br><span style="color: hsl(120, 100%, 40%);">+ 0) {</span><br><span> cbfs_file_data(prog_rdev(&bootblock), &bootblock_data);</span><br><span> </span><br><span> if (tpm_measure_region(TPM_BOOTBLOCK_PCR, prog_rdev(&bootblock),</span><br><span> "bootblock")) {</span><br><span> return VB2_ERROR_UNKNOWN;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "VBOOT: Couldn't measure %s into CRTM!",</span><br><span style="color: hsl(0, 100%, 40%);">- "bootblock");</span><br><span> } else {</span><br><span> struct region_device fmap;</span><br><span style="color: hsl(0, 100%, 40%);">- if (!fmap_locate_area_as_rdev("BOOTBLOCK", &fmap)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (fmap_locate_area_as_rdev("BOOTBLOCK", &fmap) == 0) {</span><br><span> if (tpm_measure_region(TPM_BOOTBLOCK_PCR, &fmap,</span><br><span> "bootblock")) {</span><br><span> return VB2_ERROR_UNKNOWN;</span><br><span>@@ -56,8 +73,8 @@</span><br><span> if (IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) {</span><br><span> struct cbfsf romstage_data;</span><br><span> /* measure verstage from RO */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!cbfs_boot_locate(&romstage_data, prog_name(&romstage),</span><br><span style="color: hsl(0, 100%, 40%);">- NULL)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cbfs_boot_locate(&romstage_data, prog_name(&romstage),</span><br><span style="color: hsl(120, 100%, 40%);">+ NULL) == 0) {</span><br><span> cbfs_file_data(prog_rdev(&romstage), &romstage_data);</span><br><span> </span><br><span> if (tpm_measure_region(TPM_STAGE_ROMSTAGE_PCR,</span><br><span>@@ -76,8 +93,8 @@</span><br><span> if (IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)) {</span><br><span> struct cbfsf verstage_data;</span><br><span> /* measure verstage from RO */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!cbfs_boot_locate(&verstage_data, prog_name(&verstage),</span><br><span style="color: hsl(0, 100%, 40%);">- NULL)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cbfs_boot_locate(&verstage_data, prog_name(&verstage),</span><br><span style="color: hsl(120, 100%, 40%);">+ NULL) == 0) {</span><br><span> cbfs_file_data(prog_rdev(&verstage), &verstage_data);</span><br><span> </span><br><span> if (tpm_measure_region(TPM_STAGE_VERSTAGE_PCR,</span><br><span>@@ -146,3 +163,57 @@</span><br><span> break;</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int blob_hook_region_device(const struct blob_locator locator,</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct region_device *data)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int pcr_index = TPM_UNKNOWN_PCR;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (locator.id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_BOOTSPLASH:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_ACPI_SLIC:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_ACPI_DSDT:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_ACPI_SSDT:</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_index = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_MICROCODE:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_MICROCODE_RMU:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_MRC_CACHE:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_MRC_CACHE_RW_REGION:</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_index = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_VGA_VBT:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_NVRAM_CMOS_LAYOUT:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_NVRAM_CMOS_DEFAULT:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_NVRAM_VPD:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_SIEMENS_HWLIB:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_SPD:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_MAC:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_AMD_S3NV:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_DATA_NVRAM_VPD_RO_REGION:</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_index = 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_AMD_AGESA:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_AMD_AGESA_PRE_MEM:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_AMD_AGESA_POST_MEM:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_AMD_PSP:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_INTEL_MRC:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_INTEL_FSP_S:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_INTEL_FSP_M:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_INTEL_MMA:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_NVIDIA_MTC:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_QUALCOMM_CDT:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_QUALCOMM_DDR:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_QUALCOMM_TZ:</span><br><span style="color: hsl(120, 100%, 40%);">+ case ID_CODE_QUALCOMM_RPM:</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_index = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tpm_measure_region(pcr_index, data, locator.cbfs_name) !=</span><br><span style="color: hsl(120, 100%, 40%);">+ TPM_SUCCESS) {</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24993">change 24993</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/24993"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3ddfeabd63aefec152a9bc439a415c37b814f94f </div>
<div style="display:none"> Gerrit-Change-Number: 24993 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>