<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25002">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/Kconfig: Create a power restore option<br><br>File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL<br>that's not used at all and has no control. It's also not used in the<br>build process. Remove the define from sm.c, create a true Kconfig<br>definition and use it to define if power should be restored after a power<br>failure/recovery.<br><br>BUG=b:72873003<br>TEST=Build kahlee. Use serial output to check what is being programmed<br>to RTC shadow. Build with and without selecting the Kconfig parameter.<br>Then remove serial output and leave the parameter unselected (always S5<br>at power recovery).<br><br>Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/sm.c<br>M src/soc/amd/stoneyridge/southbridge.c<br>4 files changed, 17 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/25002/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig</span><br><span>index de1cb92..d29846a 100644</span><br><span>--- a/src/soc/amd/stoneyridge/Kconfig</span><br><span>+++ b/src/soc/amd/stoneyridge/Kconfig</span><br><span>@@ -382,4 +382,11 @@</span><br><span> int</span><br><span> default 133</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_POWER_ON_AFTER_POWER_FAIL</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ If selected, after power fail power will be S0 if</span><br><span style="color: hsl(120, 100%, 40%);">+ previously at S0 else S5.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 3011af2..fae3089 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -48,6 +48,10 @@</span><br><span> #define PM_SERIRQ_MODE BIT(6)</span><br><span> #define PM_SERIRQ_ENABLE BIT(7)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define PM_RTC_SHADOW 0x5b /* state when power resumes */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM_S5_AT_POWER_RECOVERY 0x04 /* S5 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PM_RESTORE_ORIGINAL_POWER 0x07 /* S0 if previouusly at S0 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define PM_EVT_BLK 0x60</span><br><span> #define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */</span><br><span> #define PCIEXPWAK_STS BIT(14)</span><br><span>diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c</span><br><span>index 9456cbf..1ea0560 100644</span><br><span>--- a/src/soc/amd/stoneyridge/sm.c</span><br><span>+++ b/src/soc/amd/stoneyridge/sm.c</span><br><span>@@ -32,10 +32,6 @@</span><br><span> #define MAINBOARD_POWER_OFF 0</span><br><span> #define MAINBOARD_POWER_ON 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /*</span><br><span> * The southbridge enables all USB controllers by default in SMBUS Control.</span><br><span> * The southbridge enables SATA by default in SMBUS Control.</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 3d0cc74..ee4b58e 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -545,11 +545,17 @@</span><br><span> </span><br><span> void southbridge_final(void *chip_info)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t PM_RESTORED_POWER = PM_S5_AT_POWER_RECOVERY;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) {</span><br><span> agesawrapper_fchecfancontrolservice();</span><br><span> if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE))</span><br><span> enable_imc_thermal_zone();</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL))</span><br><span style="color: hsl(120, 100%, 40%);">+ PM_RESTORED_POWER = PM_RESTORE_ORIGINAL_POWER;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Power control 0x%02x\n", PM_RESTORED_POWER);</span><br><span style="color: hsl(120, 100%, 40%);">+ pm_write8(PM_RTC_SHADOW, PM_RESTORED_POWER);</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25002">change 25002</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa </div>
<div style="display:none"> Gerrit-Change-Number: 25002 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>