<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24986">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/braswell: increase LPEA fw allocation to 2MiB<br><br>Increase memory allocated for the LPEA firmware from 1MiB to 2MiB<br>to match Intel CHT reference code and fix Windows functionality.<br><br>Test: boot Windows on google/edgar, observe no error in Device Manager<br>for LPEA audio device due to BAR2 resource allocation.<br><br>Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/braswell/acpi/lpe.asl<br>M src/soc/intel/braswell/lpe.c<br>2 files changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/24986/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl</span><br><span>index 6dd73ab..145e608 100644</span><br><span>--- a/src/soc/intel/braswell/acpi/lpe.asl</span><br><span>+++ b/src/soc/intel/braswell/acpi/lpe.asl</span><br><span>@@ -26,7 +26,7 @@</span><br><span>   {</span><br><span>            Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0)</span><br><span>               Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1)</span><br><span style="color: hsl(0, 100%, 40%);">-          Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2)</span><br><span style="color: hsl(120, 100%, 40%);">+                Memory32Fixed (ReadWrite, 0, 0x00200000, BAR2)</span><br><span>               Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)</span><br><span>                 {</span><br><span>                    LPE_DMA0_IRQ</span><br><span>diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c</span><br><span>index 58b5a8d..8ec944b 100644</span><br><span>--- a/src/soc/intel/braswell/lpe.c</span><br><span>+++ b/src/soc/intel/braswell/lpe.c</span><br><span>@@ -38,7 +38,7 @@</span><br><span>  * address. Just take 1MiB @ 512MiB.</span><br><span>  */</span><br><span> #define FIRMWARE_PHYS_BASE (512 << 20)</span><br><span style="color: hsl(0, 100%, 40%);">-#define FIRMWARE_PHYS_LENGTH (1 << 20)</span><br><span style="color: hsl(120, 100%, 40%);">+#define FIRMWARE_PHYS_LENGTH (2 << 20)</span><br><span> #define FIRMWARE_PCI_REG_BASE 0xa8</span><br><span> #define FIRMWARE_PCI_REG_LENGTH 0xac</span><br><span> #define FIRMWARE_REG_BASE_C0 0x144000</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24986">change 24986</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/24986"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097 </div>
<div style="display:none"> Gerrit-Change-Number: 24986 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>