<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24984">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/haswell: Generate ACPI DMAR table<br><br>If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the<br>GFXVTBAR is only generated if the IGD is enabled.<br><br>Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/northbridge/intel/haswell/acpi.c<br>M src/northbridge/intel/haswell/haswell.h<br>M src/northbridge/intel/haswell/northbridge.c<br>3 files changed, 66 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/24984/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c</span><br><span>index e032948..9d76ba8 100644</span><br><span>--- a/src/northbridge/intel/haswell/acpi.c</span><br><span>+++ b/src/northbridge/intel/haswell/acpi.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span> #include "haswell.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/lynxpoint/pch.h></span><br><span> </span><br><span> unsigned long acpi_fill_mcfg(unsigned long current)</span><br><span> {</span><br><span>@@ -69,3 +70,59 @@</span><br><span> </span><br><span> return current;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static unsigned long acpi_fill_dmar(unsigned long current)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *const igfx_dev = dev_find_slot(0, PCI_DEVFN(2, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;</span><br><span style="color: hsl(120, 100%, 40%);">+ const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;</span><br><span style="color: hsl(120, 100%, 40%);">+ const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (igfx_dev && igfx_dev->enabled && gfxvtbar</span><br><span style="color: hsl(120, 100%, 40%);">+ && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ const unsigned long tmp = current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_dmar_drhd_fixup(tmp, current);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* VTVC0BAR has to be set, enabled, and in 32-bit space */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ const unsigned long tmp = current;</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_drhd(current,</span><br><span style="color: hsl(120, 100%, 40%);">+ DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_drhd_ds_ioapic(current,</span><br><span style="color: hsl(120, 100%, 40%);">+ 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t i;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < 8; ++i)</span><br><span style="color: hsl(120, 100%, 40%);">+ current += acpi_create_dmar_drhd_ds_msi_hpet(current,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0, PCH_HPET_PCI_BUS,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCH_HPET_PCI_SLOT, i);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_dmar_drhd_fixup(tmp, current);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long northbridge_write_acpi_tables(struct device *const dev,</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long current,</span><br><span style="color: hsl(120, 100%, 40%);">+ struct acpi_rsdp *const rsdp)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Create DMAR table only if we have VT-d capability. */</span><br><span style="color: hsl(120, 100%, 40%);">+ const u32 capid0_a = pci_read_config32(dev, CAPID0_A);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (capid0_a & VTD_DISABLE)</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_dmar_t *const dmar = (acpi_dmar_t *)current;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "ACPI: * DMAR\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);</span><br><span style="color: hsl(120, 100%, 40%);">+ current += dmar->header.length;</span><br><span style="color: hsl(120, 100%, 40%);">+ current = acpi_align_current(current);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_add_table(rsdp, dmar);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return current;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h</span><br><span>index 97ee363..5f1530a 100644</span><br><span>--- a/src/northbridge/intel/haswell/haswell.h</span><br><span>+++ b/src/northbridge/intel/haswell/haswell.h</span><br><span>@@ -230,6 +230,14 @@</span><br><span> void report_platform_info(void);</span><br><span> #endif /* !__SMM__ */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct acpi_rsdp;</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long northbridge_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+ unsigned long start, struct acpi_rsdp *rsdp);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif</span><br><span> #endif</span><br><span> #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */</span><br><span>diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c</span><br><span>index 93e711d..bbf1604 100644</span><br><span>--- a/src/northbridge/intel/haswell/northbridge.c</span><br><span>+++ b/src/northbridge/intel/haswell/northbridge.c</span><br><span>@@ -85,6 +85,7 @@</span><br><span> .init = NULL,</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span> .ops_pci_bus = pci_bus_default_ops,</span><br><span style="color: hsl(120, 100%, 40%);">+ .write_acpi_tables = northbridge_write_acpi_tables,</span><br><span> };</span><br><span> </span><br><span> static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24984">change 24984</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc </div>
<div style="display:none"> Gerrit-Change-Number: 24984 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>