<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24970">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">arch/arm64/armv8/mmu: Add support for 48bit VA<br><br>The VA space needs to be extended to support 48bit, as on Cavium SoCs<br>the MMIO starts at 1 << 47.<br><br>The following changes were done:<br>* Add a Kconfig to define the VA space on platform level and support<br> 64KB granular size for VA > 39.<br>* Decide to use either 4KB granule or 64KB granule depending on<br> supported VA space.<br>* Add helper functions for different page level sizes<br>* Add asserts to make sure that the address is withing the VA<br>* Don't use BLOCK in level1 if not on 4KB granule<br><br>Tested on Cavium SoC.<br>Needs tests on other platforms.<br><br>Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/arch/arm64/armv8/Kconfig<br>M src/arch/arm64/armv8/mmu.c<br>M src/arch/arm64/include/armv8/arch/mmu.h<br>3 files changed, 120 insertions(+), 34 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/24970/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig</span><br><span>index 2070bea..1797727 100644</span><br><span>--- a/src/arch/arm64/armv8/Kconfig</span><br><span>+++ b/src/arch/arm64/armv8/Kconfig</span><br><span>@@ -25,3 +25,10 @@</span><br><span> All ARMv8 implementations are downwards-compatible, so this does not</span><br><span> need to be changed unless specific features (e.g. new instructions)</span><br><span> are used by the SoC's coreboot code.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config ARCH_MMU_VA_BITS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 33</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Specify the amount of virtual address space that has to be supported</span><br><span style="color: hsl(120, 100%, 40%);">+ by the MMU.</span><br><span>\ No newline at end of file</span><br><span>diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c</span><br><span>index 55bd703..9dfbab1 100644</span><br><span>--- a/src/arch/arm64/armv8/mmu.c</span><br><span>+++ b/src/arch/arm64/armv8/mmu.c</span><br><span>@@ -81,11 +81,43 @@</span><br><span> return attr;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static size_t bits_per_level(const size_t level)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (level) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ return BITS_RESOLVED_PER_LVL_1;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return BITS_RESOLVED_PER_LVL_2;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3:</span><br><span style="color: hsl(120, 100%, 40%);">+ return BITS_RESOLVED_PER_LVL_3;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Invalid page table level\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static size_t addr_shift_level(const size_t level)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (level) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 1:</span><br><span style="color: hsl(120, 100%, 40%);">+ return L1_ADDR_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 2:</span><br><span style="color: hsl(120, 100%, 40%);">+ return L2_ADDR_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 3:</span><br><span style="color: hsl(120, 100%, 40%);">+ return L3_ADDR_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Invalid page table level\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Func : setup_new_table</span><br><span> * Desc : Get next free table from TTB and set it up to match old parent entry.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static uint64_t *setup_new_table(uint64_t desc, size_t xlat_size)</span><br><span style="color: hsl(120, 100%, 40%);">+static uint64_t *setup_new_table(uint64_t desc, size_t xlat_size, size_t level)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ const size_t shift = bits_per_level(level);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> while (next_free_table[0] != UNUSED_DESC) {</span><br><span> next_free_table += GRANULE_SIZE/sizeof(*next_free_table);</span><br><span> if (_ettb - (u8 *)next_free_table <= 0)</span><br><span>@@ -95,7 +127,7 @@</span><br><span> void *frame_base = (void *)(desc & XLAT_ADDR_MASK);</span><br><span> printk(BIOS_DEBUG, "Backing address range [%p:%p) with new page"</span><br><span> " table @%p\n", frame_base, frame_base +</span><br><span style="color: hsl(0, 100%, 40%);">- (xlat_size << BITS_RESOLVED_PER_LVL), next_free_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ (xlat_size << shift), next_free_table);</span><br><span> </span><br><span> if (!desc) {</span><br><span> memset(next_free_table, 0, GRANULE_SIZE);</span><br><span>@@ -118,12 +150,12 @@</span><br><span> * Desc: Check if the table entry is a valid descriptor. If not, initialize new</span><br><span> * table, update the entry and return the table addr. If valid, return the addr</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static uint64_t *get_next_level_table(uint64_t *ptr, size_t xlat_size)</span><br><span style="color: hsl(120, 100%, 40%);">+static uint64_t *get_next_level_table(uint64_t *ptr, size_t xlat_size, size_t level)</span><br><span> {</span><br><span> uint64_t desc = *ptr;</span><br><span> </span><br><span> if ((desc & DESC_MASK) != TABLE_DESC) {</span><br><span style="color: hsl(0, 100%, 40%);">- uint64_t *new_table = setup_new_table(desc, xlat_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t *new_table = setup_new_table(desc, xlat_size, level);</span><br><span> desc = ((uint64_t)new_table) | TABLE_DESC;</span><br><span> *ptr = desc;</span><br><span> }</span><br><span>@@ -151,18 +183,21 @@</span><br><span> /* L1 table lookup</span><br><span> * If VA has bits more than L2 can resolve, lookup starts at L1</span><br><span> * Assumption: we don't need L0 table in coreboot */</span><br><span style="color: hsl(0, 100%, 40%);">- if (BITS_PER_VA > L1_ADDR_SHIFT) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (CONFIG_ARCH_MMU_VA_BITS > L1_ADDR_SHIFT) {</span><br><span> if ((size >= L1_XLAT_SIZE) &&</span><br><span style="color: hsl(0, 100%, 40%);">- IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* If block address is aligned and size is greater than</span><br><span style="color: hsl(120, 100%, 40%);">+ IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT)) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (GRANULE_SIZE_SHIFT == 12)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * If block address is aligned and size is greater than</span><br><span> * or equal to size addressed by each L1 entry, we can</span><br><span style="color: hsl(0, 100%, 40%);">- * directly store a block desc */</span><br><span style="color: hsl(120, 100%, 40%);">+ * directly store a block desc</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> desc = base_addr | BLOCK_DESC | attr;</span><br><span> table[l1_index] = desc;</span><br><span> /* L2 lookup is not required */</span><br><span> return L1_XLAT_SIZE;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">- table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE);</span><br><span style="color: hsl(120, 100%, 40%);">+ table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE, 2);</span><br><span> }</span><br><span> </span><br><span> /* L2 table lookup</span><br><span>@@ -180,7 +215,7 @@</span><br><span> }</span><br><span> </span><br><span> /* L2 entry stores a table descriptor */</span><br><span style="color: hsl(0, 100%, 40%);">- table = get_next_level_table(&table[l2_index], L3_XLAT_SIZE);</span><br><span style="color: hsl(120, 100%, 40%);">+ table = get_next_level_table(&table[l2_index], L3_XLAT_SIZE, 3);</span><br><span> </span><br><span> /* L3 table lookup */</span><br><span> desc = base_addr | PAGE_DESC | attr;</span><br><span>@@ -202,19 +237,20 @@</span><br><span> * Desc : Returns the page table entry governing a specific address. */</span><br><span> static uint64_t get_pte(void *addr)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- int shift = BITS_PER_VA > L1_ADDR_SHIFT ? L1_ADDR_SHIFT : L2_ADDR_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t level = CONFIG_ARCH_MMU_VA_BITS > L1_ADDR_SHIFT ? 1 : 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t shift = addr_shift_level(level);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> uint64_t *pte = (uint64_t *)_ttb;</span><br><span> </span><br><span> while (1) {</span><br><span style="color: hsl(0, 100%, 40%);">- int index = ((uintptr_t)addr >> shift) &</span><br><span style="color: hsl(0, 100%, 40%);">- ((1UL << BITS_RESOLVED_PER_LVL) - 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ int index = ((uintptr_t)addr >> shift) & ((1UL << shift) - 1);</span><br><span> </span><br><span> if ((pte[index] & DESC_MASK) != TABLE_DESC ||</span><br><span> shift <= GRANULE_SIZE_SHIFT)</span><br><span> return pte[index];</span><br><span> </span><br><span> pte = (uint64_t *)(pte[index] & XLAT_ADDR_MASK);</span><br><span style="color: hsl(0, 100%, 40%);">- shift -= BITS_RESOLVED_PER_LVL;</span><br><span style="color: hsl(120, 100%, 40%);">+ shift = addr_shift_level(++level);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>@@ -229,6 +265,9 @@</span><br><span> uint64_t base_addr = (uintptr_t)start;</span><br><span> uint64_t temp_size = size;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ assert(base_addr < (1UL << CONFIG_ARCH_MMU_VA_BITS));</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(size < (1UL << CONFIG_ARCH_MMU_VA_BITS));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> printk(BIOS_INFO, "Mapping address range [%p:%p) as ",</span><br><span> start, start + size);</span><br><span> print_tag(BIOS_INFO, tag);</span><br><span>@@ -252,13 +291,15 @@</span><br><span> */</span><br><span> void mmu_init(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t flags;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Initially mark all table slots unused (first PTE == UNUSED_DESC). */</span><br><span> uint64_t *table = (uint64_t *)_ttb;</span><br><span> for (; _ettb - (u8 *)table > 0; table += GRANULE_SIZE/sizeof(*table))</span><br><span> table[0] = UNUSED_DESC;</span><br><span> </span><br><span> /* Initialize the root table (L1) to be completely unmapped. */</span><br><span style="color: hsl(0, 100%, 40%);">- uint64_t *root = setup_new_table(INVALID_DESC, L1_XLAT_SIZE);</span><br><span style="color: hsl(120, 100%, 40%);">+ uint64_t *root = setup_new_table(INVALID_DESC, L1_XLAT_SIZE, 1);</span><br><span> assert((u8 *)root == _ttb);</span><br><span> </span><br><span> /* Initialize TTBR */</span><br><span>@@ -268,9 +309,35 @@</span><br><span> raw_write_mair_el3(MAIR_ATTRIBUTES);</span><br><span> </span><br><span> /* Initialize TCR flags */</span><br><span style="color: hsl(0, 100%, 40%);">- raw_write_tcr_el3(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC |</span><br><span style="color: hsl(0, 100%, 40%);">- TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_64GB |</span><br><span style="color: hsl(0, 100%, 40%);">- TCR_TBI_USED);</span><br><span style="color: hsl(120, 100%, 40%);">+ flags = TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC |</span><br><span style="color: hsl(120, 100%, 40%);">+ TCR_SH0_IS | TCR_TBI_USED;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (CONFIG_ARCH_MMU_VA_BITS <= 32)</span><br><span style="color: hsl(120, 100%, 40%);">+ flags |= TCR_PS_4GB;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (CONFIG_ARCH_MMU_VA_BITS <= 36)</span><br><span style="color: hsl(120, 100%, 40%);">+ flags |= TCR_PS_64GB;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (CONFIG_ARCH_MMU_VA_BITS <= 40)</span><br><span style="color: hsl(120, 100%, 40%);">+ flags |= TCR_PS_1TB;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (CONFIG_ARCH_MMU_VA_BITS <= 42)</span><br><span style="color: hsl(120, 100%, 40%);">+ flags |= TCR_PS_4TB;</span><br><span style="color: hsl(120, 100%, 40%);">+ else if (CONFIG_ARCH_MMU_VA_BITS <= 44)</span><br><span style="color: hsl(120, 100%, 40%);">+ flags |= TCR_PS_16TB;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ flags |= TCR_PS_256TB;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (GRANULE_SIZE_SHIFT) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 12:</span><br><span style="color: hsl(120, 100%, 40%);">+ flags |= TCR_TG0_4KB;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 14:</span><br><span style="color: hsl(120, 100%, 40%);">+ flags |= TCR_TG0_16KB;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 16:</span><br><span style="color: hsl(120, 100%, 40%);">+ flags |= TCR_TG0_64KB;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ raw_write_tcr_el3(flags);</span><br><span> }</span><br><span> </span><br><span> void mmu_enable(void)</span><br><span>diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h</span><br><span>index a812073..a21c3b7 100644</span><br><span>--- a/src/arch/arm64/include/armv8/arch/mmu.h</span><br><span>+++ b/src/arch/arm64/include/armv8/arch/mmu.h</span><br><span>@@ -69,25 +69,37 @@</span><br><span> /* XLAT Table Init Attributes */</span><br><span> </span><br><span> #define VA_START 0x0</span><br><span style="color: hsl(0, 100%, 40%);">-#define BITS_PER_VA 33</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONFIG_ARCH_MMU_VA_BITS <= 39)</span><br><span> /* Granule size of 4KB is being used */</span><br><span> #define GRANULE_SIZE_SHIFT 12</span><br><span style="color: hsl(0, 100%, 40%);">-#define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define XLAT_ADDR_MASK ((1UL << BITS_PER_VA) - GRANULE_SIZE)</span><br><span style="color: hsl(0, 100%, 40%);">-#define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define BITS_RESOLVED_PER_LVL (GRANULE_SIZE_SHIFT - 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 2)</span><br><span style="color: hsl(0, 100%, 40%);">-#define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if BITS_PER_VA > L1_ADDR_SHIFT + BITS_RESOLVED_PER_LVL</span><br><span style="color: hsl(0, 100%, 40%);">- #error "BITS_PER_VA too large (we don't have L0 table support)"</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+/* Granule size of 64KB is being used */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GRANULE_SIZE_SHIFT 16</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define XLAT_ADDR_MASK ((1UL << CONFIG_ARCH_MMU_VA_BITS) - GRANULE_SIZE)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if GRANULE_SIZE_SHIFT == 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define BITS_RESOLVED_PER_LVL_1 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define BITS_RESOLVED_PER_LVL_2 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define BITS_RESOLVED_PER_LVL_3 9</span><br><span style="color: hsl(120, 100%, 40%);">+#elif GRANULE_SIZE_SHIFT == 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define BITS_RESOLVED_PER_LVL_1 6</span><br><span style="color: hsl(120, 100%, 40%);">+#define BITS_RESOLVED_PER_LVL_2 13</span><br><span style="color: hsl(120, 100%, 40%);">+#define BITS_RESOLVED_PER_LVL_3 13</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL_2 \</span><br><span style="color: hsl(120, 100%, 40%);">+ + BITS_RESOLVED_PER_LVL_3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL_3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL_1) - 1) << L1_ADDR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL_2) - 1) << L2_ADDR_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL_3) - 1) << L3_ADDR_SHIFT)</span><br><span> </span><br><span> /* These macros give the size of the region addressed by each entry of a xlat</span><br><span> table at any given level */</span><br><span>@@ -113,7 +125,7 @@</span><br><span> (0xffUL << (BLOCK_INDEX_MEM_NORMAL*8)))</span><br><span> </span><br><span> /* TCR attributes */</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCR_TOSZ (64 - BITS_PER_VA)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCR_TOSZ (64 - CONFIG_ARCH_MMU_VA_BITS)</span><br><span> </span><br><span> #define TCR_IRGN0_SHIFT 8</span><br><span> #define TCR_IRGN0_NM_NC (0x00 << TCR_IRGN0_SHIFT)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24970">change 24970</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/24970"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262 </div>
<div style="display:none"> Gerrit-Change-Number: 24970 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>