<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24964">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block/smm: Add delay(configurable) before entering S5<br><br>This change adds a configurable delay in milliseconds before SLP_EN is<br>set in SLP_SMI for S5. Reason for doing this is to avoid race between<br>SLP and power button SMIs.<br><br>On some platforms (Nami, Nautilus), it was observed that power button<br>SMI triggered by EC was competing with the SLP SMI triggered by<br>keyboard driver. Keyboard driver indicated power button press which<br>resulted in depthcharge triggering SLP_SMI, causing the AP to enter<br>S5. However, the power button press also causes the EC to send a pulse<br>on PWRBTN# line, which is debounced for 16ms before an interrupt is<br>triggered. This interrupt was generated after SLP_SMI is processed<br>which resulted in the device waking back up from S5.<br><br>This change adds a config option<br>SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is used to add a delay<br>before SLP_EN is set for S5. This change should only affect CHROMEOS<br>boards as the config option will be 0 in other cases.<br><br>BUG=b:74083107<br>TEST=Verified that nami, nautilus do not wake back from S5 on power<br>button press at dev mode screen.<br><br>Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7<br>Signed-off-by: Furquan Shaikh <furquan@google.com><br>---<br>M src/soc/intel/common/block/smm/Kconfig<br>M src/soc/intel/common/block/smm/smihandler.c<br>2 files changed, 14 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/24964/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig</span><br><span>index 0355780..909382e 100644</span><br><span>--- a/src/soc/intel/common/block/smm/Kconfig</span><br><span>+++ b/src/soc/intel/common/block/smm/Kconfig</span><br><span>@@ -7,3 +7,12 @@</span><br><span> bool</span><br><span> help</span><br><span> Intel Processor trap flag if it is supported</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 100 if CHROMEOS</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Time in milliseconds that SLP_SMI for S5 waits for before</span><br><span style="color: hsl(120, 100%, 40%);">+ enabling sleep. This is required to avoid any race between</span><br><span style="color: hsl(120, 100%, 40%);">+ SLP_SMI and PWRBTN SMI.</span><br><span>diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c</span><br><span>index 81ff3eb..fc908c2 100644</span><br><span>--- a/src/soc/intel/common/block/smm/smihandler.c</span><br><span>+++ b/src/soc/intel/common/block/smm/smihandler.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <elog.h></span><br><span> #include <intelblocks/fast_spi.h></span><br><span>@@ -219,6 +220,10 @@</span><br><span> pmc_soc_restore_power_failure();</span><br><span> /* also iterates over all bridges on bus 0 */</span><br><span> busmaster_disable_on_bus(0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ mdelay(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS);</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_clear_pm1_status();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> break;</span><br><span> default:</span><br><span> printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24964">change 24964</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/24964"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7 </div>
<div style="display:none"> Gerrit-Change-Number: 24964 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>