<p>Andy Yeh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/24910">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/nautilus: Modify the XTDV = 210 due to different OSC from Poppy<br><br>It is to change MCLK output in 19.2Mhz (currently 23.04Mhz) because<br>nautilus uses different OSC for TI PMIC.<br><br>According to PMIC datasheet (tps68470), the MCLK for camera depends on<br>the frequency of OSC. In poppy, the frequency of OSC is 20 MHz, the<br>PLL_REF_CLK = 20M / [XTDV (170) + 30] = 100kHz.<br>If we want to keep the PLL_REF_CLK in nautilus with 24 MHz OSC, we<br>should change XDTV to 210.<br><br>BUG=b:73987684<br>TEST: Verified the MIPI camera fps on DUT board.<br>TODO: If OEM will fix OSC on next build. This patch could be reverted.<br><br>Change-Id: Ia93bee1fc07434c13a5fa4227e100ddaff2de74a<br>Signed-off-by: Andy Yeh <andy.yeh@intel.com><br>---<br>M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl<br>1 file changed, 6 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/24910/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl</span><br><span>index b74fba9..3210da1d 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl</span><br><span>+++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl</span><br><span>@@ -354,7 +354,13 @@</span><br><span>                                       /* Set the PLL_REF_CLK cyles */</span><br><span>                                      PSWR = 19</span><br><span>                                    /* Set the reference crystal divider */</span><br><span style="color: hsl(120, 100%, 40%);">+                                       /* SW Workaround to generate 19.2Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+                                  MCLK on Nautilus */</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NAUTILUS)</span><br><span style="color: hsl(120, 100%, 40%);">+                                     XTDV = 210</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span>                                    XTDV = 170</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>                                   /* Set PLL feedback divider */</span><br><span>                                       PLDV = 32</span><br><span>                                    /* Set PLL output divider for HCLK_A */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/24910">change 24910</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/24910"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia93bee1fc07434c13a5fa4227e100ddaff2de74a </div>
<div style="display:none"> Gerrit-Change-Number: 24910 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Andy Yeh <andy.yeh@intel.corp-partner.google.com> </div>