<p>Zhongze Hu would like Zhongze Hu to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/23845">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">fizz: Enable PCIe port 11, 12 on device tree<br><br>Our CFM daughter card would like to use individual PCIe lanes for two<br>different devices on the card.<br>dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b connector<br>on fizz to meet the requirement. We also need to enable the ports on device tree.<br><br>BUG=b:72523836<br>TEST=none<br>BRANCH=fizz<br>CQ-DEPEND=CL:*571936<br><br>Change-Id: Icded9850d833752680e0174b6c476e657817b319<br>Reviewed-on: https://chromium-review.googlesource.com/923867<br>Commit-Ready: Zhongze Hu <frankhu@google.com><br>Tested-by: Zhongze Hu <frankhu@google.com><br>Reviewed-by: Shelley Chen <shchen@chromium.org><br>Reviewed-on: https://chromium-review.googlesource.com/924860<br>Commit-Queue: Shelley Chen <shchen@chromium.org><br>Tested-by: Shelley Chen <shchen@chromium.org><br>---<br>M src/mainboard/google/fizz/devicetree.cb<br>1 file changed, 28 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/23845/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb</span><br><span>index 3b084ff..5eeb03c 100644</span><br><span>--- a/src/mainboard/google/fizz/devicetree.cb</span><br><span>+++ b/src/mainboard/google/fizz/devicetree.cb</span><br><span>@@ -228,6 +228,32 @@</span><br><span> # RP 9 uses uses CLK SRC 2</span><br><span> register "PcieRpClkSrcNumber[8]" = "2"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root port 11 for BtoB.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 11 uses SRCCLKREQ2#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[10]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 11, Enable Advanced Error Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpAdvancedErrorReporting[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 11, Enable Latency Tolerance Reporting Mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpLtrEnable[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 11 uses uses CLK SRC 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[10]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root port 12 for BtoB.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 12 uses SRCCLKREQ2#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[11]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 12, Enable Advanced Error Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpAdvancedErrorReporting[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 12, Enable Latency Tolerance Reporting Mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpLtrEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 12 uses uses CLK SRC 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[11]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C</span><br><span> register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear</span><br><span> register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front</span><br><span>@@ -351,8 +377,8 @@</span><br><span> end</span><br><span> end # PCI Express Port 9 for BtoB</span><br><span> device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(0, 100%, 40%);">- device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 on end # PCI Express Port 12</span><br><span> device pci 1e.0 on end # UART #0</span><br><span> device pci 1e.1 off end # UART #1</span><br><span> device pci 1e.2 on</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23845">change 23845</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icded9850d833752680e0174b6c476e657817b319 </div>
<div style="display:none"> Gerrit-Change-Number: 23845 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Zhongze Hu <frankhu@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Zhongze Hu <frankhu@google.com> </div>