<p>Justin TerAvest has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23828">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Add readable macros for GPIO<br><br>This commit defines a set of macros for defining GPIO configuration that<br>are easier to read than the raw iomux function values used today.<br><br>TEST=None<br>BUG=b:72875858<br><br>Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8<br>Signed-off-by: Justin TerAvest <teravest@chromium.org><br>---<br>M src/soc/amd/stoneyridge/include/soc/gpio.h<br>1 file changed, 201 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/23828/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h</span><br><span>index 84a4e84..5e5055a 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/gpio.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h</span><br><span>@@ -142,6 +142,207 @@</span><br><span> #define GPIO_147 147</span><br><span> #define GPIO_148 148</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* IOMUX function names and values generated from BKDG. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_0_PWR_BTN_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_0_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_1_SYS_RESET_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_1_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_2_WAKE_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_2_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_3_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_4_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_5_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_5_DEVSLP0_S5 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_6_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_6_LDT_RST_L 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_7_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_7_LDT_PWROK 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_8_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_8_SerPortTX_OUT 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_9_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_9_SerPortRX_OUT 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_10_S0A3_GPIO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_10_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_11_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_11_USB_OC7_L 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_12_IR_LED_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_12_LLB_L 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_12_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_13_USB_OC5_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_13_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_14_USB_OC6_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_14_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_15_IR_RX1 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_15_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_16_USB_OC0_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_16_TRST_L 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_16_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_17_USB_OC1_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_17_TDI 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_17_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_18_USB_OC2_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_18_TCK 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_18_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_19_SCL1 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_19_I2C3_SCL 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_19_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_20_SDA1 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_20_I2C3_SDA 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_20_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_21_LPC_PD_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_21_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_22_LPC_PME_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_22_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_23_USB_OC4_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_23_IR_RX0 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_23_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_24_USB_OC3_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_24_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_25_SD0_CD 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_25_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_26_PCIE_RST_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_26_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_39_VDDGFX_PD 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_39_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_40_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_42_S5_MUX_CTRL 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_42_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_64_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_65_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_66_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_66_ShutDown_L 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_67_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_67_DEVSLP0 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_68_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_68_SGPIO_CLK 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_69_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_69_SGPIO_LOAD 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_70_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_70_DEVSLP1 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_71_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_71_SGPIO_DATAOUT 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_72_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_72_SGPIO_DATAIN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_74_LPCCLK0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_74_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_75_LPCCLK1 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_75_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_76_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_76_SPI_TPM_CS_L 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_84_FANIN0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_84_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_85_FANOUT0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_85_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_86_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_87_SERIRQ 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_87_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_88_LPC_CLKRUN_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_88_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_89_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_90_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_91_SPKR 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_91_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_92_CLK_REQ0_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_92_SATA_IS0_L 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_92_SATA_ZP0_L 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_92_GPIOxx 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_93_SD0_LED 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_93_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_95_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_96_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_97_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_98_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_99_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_100_GPIOxx 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_101_SD0_WP 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_101_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_102_SD0_PWR_CTRL 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_102_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_113_SCL0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_113_I2C2_SCL 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_113_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_114_SDA0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_114_I2C2_SDA 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_114_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_115_CLK_REQ1_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_115_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_116_CLK_REQ2_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_116_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_117_ESPI_CLK 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_117_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_118_SPI_CS1_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_118_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_119_SPI_CS2_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_119_ESPI_CS_L 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_119_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_120_ESPI_DAT1 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_120_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_121_ESPI_DAT0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_121_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_122_ESPI_DAT2 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_122_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_126_GA20IN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_126_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_129_KBRST_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_129_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_130_SATA_ACT_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_130_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_131_CLK_REQ3_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_131_SATA_IS1_L 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_131_SATA_ZP1_L 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_131_GPIOxx 3</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_132_CLK_REQG_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_132_OSCIN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_132_GPIOxx 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_133_ESPI_DAT3 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_133_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_135_UART0_CTS_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_135_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_136_UART0_RXD 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_136_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_137_UART0_RTS_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_137_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_138_UART0_TXD 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_138_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_139_UART0_INTR 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_139_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_140_UART1_CTS_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_140_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_141_UART1_RXD 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_141_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_142_UART1_RTS_L 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_142_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_143_UART1_TXD 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_143_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_144_UART1_INTR 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_144_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_145_I2C0_SCL 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_145_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_146_I2C0_SDA 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_146_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_147_I2C1_SCL 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_147_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_148_I2C1_SDA 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_148_GPIOxx 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_OUTPUT_OUT_HIGH (FCH_GPIO_OUTPUT_ENABLE | FCH_GPIO_OUTPUT_VALUE)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_OUTPUT_OUT_LOW FCH_GPIO_OUTPUT_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PULL_PULL_UP FCH_GPIO_PULL_UP_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PULL_PULL_DOWN FCH_GPIO_PULL_DOWN_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PULL_PULL_NONE 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Native function pad configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PAD_NF(pin, func, pull) \</span><br><span style="color: hsl(120, 100%, 40%);">+ {pin, pin ## _ ## func, GPIO_PULL ## _ ## pull}</span><br><span style="color: hsl(120, 100%, 40%);">+/* General purpose input pad configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PAD_GPI(pin, pull) \</span><br><span style="color: hsl(120, 100%, 40%);">+ {pin, pin ## _ ## GPIOxx, GPIO_PULL ## _ ## pull}</span><br><span style="color: hsl(120, 100%, 40%);">+/* General purpose output pad configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PAD_GPO(pin, direction) \</span><br><span style="color: hsl(120, 100%, 40%);">+ {pin, pin ## _ ## GPIOxx, GPIO_OUTPUT ## _ ## direction}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> typedef uint32_t gpio_t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif /* __ACPI__ */</span><br><span> #endif /* __STONEYRIDGE_GPIO_H__ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23828">change 23828</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23828"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8 </div>
<div style="display:none"> Gerrit-Change-Number: 23828 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Justin TerAvest <teravest@chromium.org> </div>