<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23824">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode<br><br>TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree.<br><br>Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/finalize.c<br>M src/soc/intel/cannonlake/include/soc/pcr_ids.h<br>M src/soc/intel/cannonlake/smihandler.c<br>3 files changed, 92 insertions(+), 47 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/23824/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c</span><br><span>index df4def2..37399a6 100644</span><br><span>--- a/src/soc/intel/cannonlake/finalize.c</span><br><span>+++ b/src/soc/intel/cannonlake/finalize.c</span><br><span>@@ -33,49 +33,12 @@</span><br><span> #include <soc/systemagent.h></span><br><span> #include <stdlib.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PSF_BASE_ADDRESS 0x300</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSFX_T0_SHDW_PCIEN 0x1C</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */</span><br><span> #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */</span><br><span> #define CAM_CLK_EN (1 << 1)</span><br><span> #define MIPI_CLK (1 << 0)</span><br><span> #define HDPLL_CLK (0 << 0)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id));</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void disable_sideband_access(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t mask;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = PCH_DEV_P2SB;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Remove the host accessing right to PSF register range. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */</span><br><span style="color: hsl(0, 100%, 40%);">- mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);</span><br><span style="color: hsl(0, 100%, 40%);">- pch_configure_endpoints(dev, 5, mask);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_disable_heci(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,</span><br><span style="color: hsl(0, 100%, 40%);">- PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);</span><br><span style="color: hsl(0, 100%, 40%);">- disable_sideband_access();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void pch_enable_isclk(void)</span><br><span> {</span><br><span> pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);</span><br><span>@@ -89,20 +52,11 @@</span><br><span> if (!dev)</span><br><span> return;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (config->HeciEnabled && !config->pch_isclk)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!config->pch_isclk)</span><br><span> return;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* unhide p2sb device */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCH_P2SB_E0 + 1, 0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->HeciEnabled == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- pch_disable_heci();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> if (config->pch_isclk)</span><br><span> pch_enable_isclk();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* hide p2sb device */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCH_P2SB_E0 + 1, 1);</span><br><span> }</span><br><span> </span><br><span> static void pch_finalize(void)</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h</span><br><span>index b77eab8..04ea147 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h</span><br><span>@@ -25,6 +25,7 @@</span><br><span> #define PID_GPIOCOM0 0x6e</span><br><span> #define PID_DMI 0x88</span><br><span> #define PID_PSTH 0x89</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_CSME0 0x90</span><br><span> #define PID_ISCLK 0xad</span><br><span> #define PID_PSF1 0xba</span><br><span> #define PID_PSF2 0xbb</span><br><span>diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c</span><br><span>index f40e81d..dac57ac 100644</span><br><span>--- a/src/soc/intel/cannonlake/smihandler.c</span><br><span>+++ b/src/soc/intel/cannonlake/smihandler.c</span><br><span>@@ -15,16 +15,106 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span> #include <intelblocks/fast_spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span> #include <intelblocks/smihandler.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span> #include <soc/pm.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define CSME0_FBE 0xf</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSME0_BAR 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSME0_FID 0xb0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> const struct smm_save_state_ops *get_smm_save_state_ops(void)</span><br><span> {</span><br><span> return &em64t101_smm_ops;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void disable_sideband_access(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Remove the host accessing right to PSF register range. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */</span><br><span style="color: hsl(120, 100%, 40%);">+ mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_configure_endpoints(dev, 5, mask);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_disable_heci(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev = PCH_DEV_P2SB;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pcr_sbi_msg sbi_msg;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pcr_sbi_msg *msg = &sbi_msg;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t data32 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t response;</span><br><span style="color: hsl(120, 100%, 40%);">+ int status;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* unhide p2sb device */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, PCH_P2SB_E0 + 1, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* disable heci#1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ msg->pid = PID_CSME0;</span><br><span style="color: hsl(120, 100%, 40%);">+ msg->offset = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ msg->opcode = PCR_WRITE;</span><br><span style="color: hsl(120, 100%, 40%);">+ msg->is_posted = false;</span><br><span style="color: hsl(120, 100%, 40%);">+ msg->fast_byte_enable = CSME0_FBE;</span><br><span style="color: hsl(120, 100%, 40%);">+ msg->bar = CSME0_BAR;</span><br><span style="color: hsl(120, 100%, 40%);">+ msg->fid = CSME0_FID;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bit 0: Set to make HECI#1 Function disable */</span><br><span style="color: hsl(120, 100%, 40%);">+ data32 |= 0x1;</span><br><span style="color: hsl(120, 100%, 40%);">+ response = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Send SBI command to make HECI#1 function disable */</span><br><span style="color: hsl(120, 100%, 40%);">+ status = pcr_execute_sideband_msg (msg, &data32, &response);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure to Lock SBI interface after this command */</span><br><span style="color: hsl(120, 100%, 40%);">+ disable_sideband_access(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* hide p2sb device */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, PCH_P2SB_E0 + 1, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Specific SOC SMI handler during ramstage finalize phase</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * BIOS can't make CSME function disable as is due to POSTBOOT_SAI</span><br><span style="color: hsl(120, 100%, 40%);">+ * restriction in place from CNP chipset. Hence create SMI Handler to</span><br><span style="color: hsl(120, 100%, 40%);">+ * perform CSME function disabling logic during SMM mode.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void smihandler_soc_at_finalize(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ return ;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (config->HeciEnabled == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_disable_heci();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void smihandler_soc_check_illegal_access(uint32_t tco_sts)</span><br><span> {</span><br><span> if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23824">change 23824</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23824"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c </div>
<div style="display:none"> Gerrit-Change-Number: 23824 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>