<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23809">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block/pcr: Function for executing PCH SBI message<br><br>This function to perform SBI communication<br><br>Input:<br> * PID: Port ID of the SBI message<br> * Offset: Register offset of the SBI message<br> * Opcode: Opcode<br> * Posted: Posted message<br> * Fast_Byte_Enable: First Byte Enable<br> * BAR: base address<br> * FID: Function ID<br> * Data: Read/Write Data<br> * Response: Response<br><br>Output:<br> * 0: SBI message is Successfully completed<br> * -1: SBI message failure<br><br>Change-Id: I4e49311564e20cedbfabaaceaf5f72c480e5ea26<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/common/block/include/intelblocks/pcr.h<br>M src/soc/intel/common/block/pcr/pcr.c<br>2 files changed, 233 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/23809/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/include/intelblocks/pcr.h b/src/soc/intel/common/block/include/intelblocks/pcr.h</span><br><span>index cfe0015..0127f17 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/pcr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/pcr.h</span><br><span>@@ -38,6 +38,39 @@</span><br><span> void pcr_or16(uint8_t pid, uint16_t offset, uint16_t ordata);</span><br><span> void pcr_or8(uint8_t pid, uint16_t offset, uint8_t ordata);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* SBI command */</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ MEM_READ = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ MEM_WRITE = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_CONFIG_READ = 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCI_CONFIG_WRITE = 5,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCR_READ = 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCR_WRITE = 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_LOCK_UNLOCK = 13,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * API to perform sideband communication</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Input:</span><br><span style="color: hsl(120, 100%, 40%);">+ * PID: Port ID of the SBI message</span><br><span style="color: hsl(120, 100%, 40%);">+ * Offset: Register offset of the SBI message</span><br><span style="color: hsl(120, 100%, 40%);">+ * Opcode: Opcode</span><br><span style="color: hsl(120, 100%, 40%);">+ * Posted: Posted message</span><br><span style="color: hsl(120, 100%, 40%);">+ * Fast_Byte_Enable: First Byte Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * BAR: base address</span><br><span style="color: hsl(120, 100%, 40%);">+ * FID: Function ID</span><br><span style="color: hsl(120, 100%, 40%);">+ * Data: Read/Write Data</span><br><span style="color: hsl(120, 100%, 40%);">+ * Response: Response</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Output:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0: SBI message is Successfully completed</span><br><span style="color: hsl(120, 100%, 40%);">+ * -1: SBI message failure</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int pcr_execute_sideband_msg(uint8_t pid, uint32_t offset, uint8_t opcode,</span><br><span style="color: hsl(120, 100%, 40%);">+ bool is_posted, uint16_t fast_byte_enable, uint16_t bar,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t fid, uint32_t *data, uint8_t *response);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Get the starting address of the port's registers. */</span><br><span> void *pcr_reg_address(uint8_t pid, uint16_t offset);</span><br><span> #endif /* if !defined(__ACPI__) */</span><br><span>diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c</span><br><span>index 4264cdf..28c93c2 100644</span><br><span>--- a/src/soc/intel/common/block/pcr/pcr.c</span><br><span>+++ b/src/soc/intel/common/block/pcr/pcr.c</span><br><span>@@ -15,13 +15,41 @@</span><br><span> </span><br><span> #include <arch/io.h></span><br><span> #include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span> #include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span> #include <soc/pcr_ids.h></span><br><span> </span><br><span> #if !defined(CONFIG_PCR_BASE_ADDRESS) || (CONFIG_PCR_BASE_ADDRESS == 0)</span><br><span> #error "PCR_BASE_ADDRESS need to be non-zero!"</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* P2SB PCI configuration register */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_ADDR 0xd0</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_DESTID 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_DATA 0xd4</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_STATUS 0xd8</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bit 15:8 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_OPCODE 8</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bit 7 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_POSTED 7</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bit 2-1 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_STATUS_SUCCESS 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_STATUS_NOT_SUPPORTED 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_STATUS_POWERED_DOWN 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_STATUS_MULTI_CAST_MIXED 3</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bit 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_STATUS_READY 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_STATUS_BUSY 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_ROUTE_IDEN 0xda</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bit 15-12 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_FBE 12</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bit 10-8 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_BAR 8</span><br><span style="color: hsl(120, 100%, 40%);">+/* Bit 7-0 */</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_FID 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define P2SB_CR_SBI_EXT_ADDR 0xdc</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void *__pcr_reg_address(uint8_t pid, uint16_t offset)</span><br><span> {</span><br><span> uintptr_t reg_addr;</span><br><span>@@ -178,3 +206,175 @@</span><br><span> data8 |= ordata;</span><br><span> pcr_write8(pid, offset, data8);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int pcr_check_for_timeout(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t timeout;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ timeout = 0xFFFFFFF;</span><br><span style="color: hsl(120, 100%, 40%);">+ while (timeout > 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((pci_read_config16 (dev, P2SB_CR_SBI_STATUS) &</span><br><span style="color: hsl(120, 100%, 40%);">+ P2SB_CR_SBI_STATUS_BUSY) == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ timeout--;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Timed out */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (timeout == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * API to perform sideband communication</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Input:</span><br><span style="color: hsl(120, 100%, 40%);">+ * PID: Port ID of the SBI message</span><br><span style="color: hsl(120, 100%, 40%);">+ * Offset: Register offset of the SBI message</span><br><span style="color: hsl(120, 100%, 40%);">+ * Opcode: Opcode</span><br><span style="color: hsl(120, 100%, 40%);">+ * Posted: Posted message</span><br><span style="color: hsl(120, 100%, 40%);">+ * Fast_Byte_Enable: First Byte Enable</span><br><span style="color: hsl(120, 100%, 40%);">+ * BAR: base address</span><br><span style="color: hsl(120, 100%, 40%);">+ * FID: Function ID</span><br><span style="color: hsl(120, 100%, 40%);">+ * Data: Read/Write Data</span><br><span style="color: hsl(120, 100%, 40%);">+ * Response: Response</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Output:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0: SBI message is Successfully completed</span><br><span style="color: hsl(120, 100%, 40%);">+ * -1: SBI message failure</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int pcr_execute_sideband_msg(uint8_t pid, uint32_t offset, uint8_t opcode,</span><br><span style="color: hsl(120, 100%, 40%);">+ bool is_posted, uint16_t fast_byte_enable, uint16_t bar,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t fid, uint32_t *data, uint8_t *response)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev = PCH_DEV_P2SB;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t sbi_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t sbi_status;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch(opcode) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_READ:</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_WRITE:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_CONFIG_READ:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_CONFIG_WRITE:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCR_READ:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCR_WRITE:</span><br><span style="color: hsl(120, 100%, 40%);">+ case GPIO_LOCK_UNLOCK:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "SBI Failure: Wrong Input!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pci_read_config16(dev, PCI_VENDOR_ID) == 0xffff) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "SBI Failure: P2SB device Hidden!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * BWG Section 2.2.1</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1. Poll P2SB PCI offset D8h[0] = 0b</span><br><span style="color: hsl(120, 100%, 40%);">+ * Make sure the previous opeartion is completed.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pcr_check_for_timeout(dev)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "SBI Failure: Time Out!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initial Response status */</span><br><span style="color: hsl(120, 100%, 40%);">+ *response = 0xFF;</span><br><span style="color: hsl(120, 100%, 40%);">+ sbi_status = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2. Write P2SB PCI offset D0h[31:0] with Address</span><br><span style="color: hsl(120, 100%, 40%);">+ * and Destination Port ID</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32 (dev, P2SB_CR_SBI_ADDR,</span><br><span style="color: hsl(120, 100%, 40%);">+ (uint32_t) ((pid << P2SB_CR_SBI_DESTID) | (uint16_t) offset));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * 3. Write P2SB PCI offset DCh[31:0] with extended address,</span><br><span style="color: hsl(120, 100%, 40%);">+ * which is expected to be 0 in CNL PCH</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32 (dev, P2SB_CR_SBI_EXT_ADDR,</span><br><span style="color: hsl(120, 100%, 40%);">+ (uint32_t) (offset >> 16));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * 4. Set P2SB PCI offset D8h[15:8] = 00000110b for read</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set P2SB PCI offset D8h[15:8] = 00000111b for write</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set SBISTAT[15:8] to the opcode passed in</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set SBISTAT[7] to the posted passed in</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ sbi_status = pci_read_config16 (dev, P2SB_CR_SBI_STATUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ sbi_status &= ~(0xFF00 | (1 << P2SB_CR_SBI_POSTED));</span><br><span style="color: hsl(120, 100%, 40%);">+ sbi_status |= ((opcode << P2SB_CR_SBI_OPCODE) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (is_posted << P2SB_CR_SBI_POSTED));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16 (dev, P2SB_CR_SBI_STATUS, sbi_status);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * 5. Write P2SB PCI offset DAh[15:0] = F000h</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set RID[15:0] = Fbe << 12 | Bar << 8 | Fid</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16 (dev, P2SB_CR_SBI_ROUTE_IDEN, (uint16_t) (</span><br><span style="color: hsl(120, 100%, 40%);">+ ((fast_byte_enable & 0x000F) << P2SB_CR_SBI_FBE) |</span><br><span style="color: hsl(120, 100%, 40%);">+ ((bar & 0x0007) << P2SB_CR_SBI_BAR) |</span><br><span style="color: hsl(120, 100%, 40%);">+ (fid & 0x00FF)));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch(opcode) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_WRITE:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_CONFIG_WRITE:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCR_WRITE:</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * 6. Write P2SB PCI offset D4h[31:0] with the</span><br><span style="color: hsl(120, 100%, 40%);">+ * intended data accordingly</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ sbi_data = *data;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32 (dev, P2SB_CR_SBI_DATA, sbi_data);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 6. Write P2SB PCI offset D4h[31:0] with dummy data */</span><br><span style="color: hsl(120, 100%, 40%);">+ sbi_data = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32 (dev, P2SB_CR_SBI_DATA, sbi_data);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * 7. Set P2SB PCI offset D8h[0] = 1b, Poll P2SB PCI offset D8h[0] = 0b</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set SBISTAT[0] = 1b, trigger the SBI operation</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ sbi_status = pci_read_config16 (dev, P2SB_CR_SBI_STATUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ sbi_status |= P2SB_CR_SBI_STATUS_BUSY;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16 (dev, P2SB_CR_SBI_STATUS, sbi_status);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Poll SBISTAT[0] = 0b, Polling for Busy bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pcr_check_for_timeout(dev)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "SBI Failure: Time Out!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * 8. Check if P2SB PCI offset D8h[2:1] = 00b for</span><br><span style="color: hsl(120, 100%, 40%);">+ * successful transaction</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ *response = (uint8_t) ((sbi_status & 0x0006) >> 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (*response == P2SB_CR_SBI_STATUS_SUCCESS) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch(opcode) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case MEM_READ:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_CONFIG_READ:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCR_READ:</span><br><span style="color: hsl(120, 100%, 40%);">+ sbi_data = pci_read_config32 (dev, P2SB_CR_SBI_DATA);</span><br><span style="color: hsl(120, 100%, 40%);">+ *data = sbi_data;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "SBI Failure: Transaction Failure!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23809">change 23809</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4e49311564e20cedbfabaaceaf5f72c480e5ea26 </div>
<div style="display:none"> Gerrit-Change-Number: 23809 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>