<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23797">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">arch/riscv: Pass the bootrom-provided FDT to the payload<br><br>The RISC-V boot protocol foresees that at every stage boundary (bootrom<br>to boot loader, boot loader -> OS), register a0 contains the Hart ID and<br>a1 contains the physical address of the Flattened Device Tree that the<br>stage shall use.<br><br>As a first step, pass the bootrom-provided FDT to the payload,<br>unmodified.<br><br>Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/arch/riscv/boot.c<br>M src/arch/riscv/bootblock.S<br>A src/arch/riscv/include/arch/boot.h<br>M src/arch/riscv/payload.S<br>M src/arch/riscv/stages.c<br>5 files changed, 78 insertions(+), 16 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/23797/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c</span><br><span>index b73f3ca..d7233fe 100644</span><br><span>--- a/src/arch/riscv/boot.c</span><br><span>+++ b/src/arch/riscv/boot.c</span><br><span>@@ -15,20 +15,35 @@</span><br><span> </span><br><span> #include <program_loading.h></span><br><span> #include <vm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/boot.h></span><br><span> #include <arch/encoding.h></span><br><span> #include <rules.h></span><br><span> #include <console/console.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * A pointer to the Flattened Device Tree passed to coreboot by the boot ROM.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Presumably this FDT is also in ROM.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This pointer is only used in ramstage!</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+const void *rom_fdt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void arch_prog_run(struct prog *prog)</span><br><span> {</span><br><span> void (*doit)(void *) = prog_entry(prog);</span><br><span style="color: hsl(0, 100%, 40%);">- void riscvpayload(const char *configstring, void *payload);</span><br><span style="color: hsl(0, 100%, 40%);">- const char *config = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ void riscvpayload(const void *fdt, void *payload);</span><br><span> </span><br><span> if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Config string: '%s'\n", config);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * FIXME: This is wrong and will crash. Linux can't (in early</span><br><span style="color: hsl(120, 100%, 40%);">+ * boot) access memory that's before its own loading address.</span><br><span style="color: hsl(120, 100%, 40%);">+ * We need to copy the FDT to a place where Linux can access it.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ const void *fdt = rom_fdt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_SPEW, "FDT is at %p\n", fdt);</span><br><span> printk(BIOS_SPEW, "OK, let's go\n");</span><br><span style="color: hsl(0, 100%, 40%);">- riscvpayload(config, doit);</span><br><span style="color: hsl(120, 100%, 40%);">+ riscvpayload(fdt, doit);</span><br><span> }</span><br><span> </span><br><span> doit(prog_entry_arg(prog));</span><br><span>diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S</span><br><span>index 43bca90..0b5a2b2 100644</span><br><span>--- a/src/arch/riscv/bootblock.S</span><br><span>+++ b/src/arch/riscv/bootblock.S</span><br><span>@@ -25,7 +25,14 @@</span><br><span> .globl _start</span><br><span> _start:</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ # The boot ROM may pass the following arguments to coreboot:</span><br><span style="color: hsl(120, 100%, 40%);">+ # a0: the value of mhartid</span><br><span style="color: hsl(120, 100%, 40%);">+ # a1: a pointer to the flattened devicetree</span><br><span style="color: hsl(120, 100%, 40%);">+ #</span><br><span style="color: hsl(120, 100%, 40%);">+ # Preserve only the FDT pointer. We can query mhartid ourselves at any</span><br><span style="color: hsl(120, 100%, 40%);">+ # time.</span><br><span style="color: hsl(120, 100%, 40%);">+ #</span><br><span style="color: hsl(120, 100%, 40%);">+ csrw mscratch, a1</span><br><span> </span><br><span> # N.B. This only works on low 4G of the address space</span><br><span> # and the stack must be page-aligned.</span><br><span>diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h</span><br><span>new file mode 100644</span><br><span>index 0000000..24c1bed</span><br><span>--- /dev/null</span><br><span>+++ b/src/arch/riscv/include/arch/boot.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Jonathan Neuschäfer</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define ARCH_RISCV_INCLUDE_ARCH_BOOT_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+extern const void *rom_fdt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S</span><br><span>index a189adf..1b8cb96 100644</span><br><span>--- a/src/arch/riscv/payload.S</span><br><span>+++ b/src/arch/riscv/payload.S</span><br><span>@@ -1,6 +1,9 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Google Inc</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Jonathan Neuschäfer</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span> * the Free Software Foundation; version 2 of the License.</span><br><span>@@ -11,17 +14,22 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-// "return" to a payload pointed to by a1 with</span><br><span style="color: hsl(0, 100%, 40%);">-// an M-mode pointer (or, to upper levels, physical address)</span><br><span style="color: hsl(0, 100%, 40%);">-// to the config string in a0.</span><br><span style="color: hsl(120, 100%, 40%);">+// "return" to a payload. a0: FDT, a1: entry point</span><br><span> .global riscvpayload</span><br><span> riscvpayload:</span><br><span style="color: hsl(0, 100%, 40%);">- mv t0,a1</span><br><span style="color: hsl(0, 100%, 40%);">- csrw mepc, t0</span><br><span style="color: hsl(0, 100%, 40%);">- csrr t0, mstatus</span><br><span style="color: hsl(0, 100%, 40%);">- li t1, ~(3<<11)</span><br><span style="color: hsl(0, 100%, 40%);">- and t0, t0, t1</span><br><span style="color: hsl(0, 100%, 40%);">- li t2, (1<<11)</span><br><span style="color: hsl(0, 100%, 40%);">- or t0, t0, t2</span><br><span style="color: hsl(0, 100%, 40%);">- csrw mstatus, t0</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Load the entry point */</span><br><span style="color: hsl(120, 100%, 40%);">+ mv t0, a1</span><br><span style="color: hsl(120, 100%, 40%);">+ csrw mepc, t0</span><br><span style="color: hsl(120, 100%, 40%);">+ csrr t0, mstatus</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set mstatus.MPP (the previous privilege mode) to supervisor mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ li t1, ~(3<<11)</span><br><span style="color: hsl(120, 100%, 40%);">+ and t0, t0, t1</span><br><span style="color: hsl(120, 100%, 40%);">+ li t2, (1<<11)</span><br><span style="color: hsl(120, 100%, 40%);">+ or t0, t0, t2</span><br><span style="color: hsl(120, 100%, 40%);">+ csrw mstatus, t0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Pass the right arguments and jump! */</span><br><span style="color: hsl(120, 100%, 40%);">+ mv a1, a0</span><br><span style="color: hsl(120, 100%, 40%);">+ csrr a0, mhartid</span><br><span> mret</span><br><span>diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c</span><br><span>index 053fd76..8075476 100644</span><br><span>--- a/src/arch/riscv/stages.c</span><br><span>+++ b/src/arch/riscv/stages.c</span><br><span>@@ -24,9 +24,20 @@</span><br><span> * linker script.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/boot.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/encoding.h></span><br><span> #include <arch/stages.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <rules.h></span><br><span> </span><br><span> void stage_entry(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Save the FDT pointer before entering ramstage, because mscratch</span><br><span style="color: hsl(120, 100%, 40%);">+ * might be overwritten in the trap handler, and there is code in</span><br><span style="color: hsl(120, 100%, 40%);">+ * ramstage that generates misaligned access faults.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ENV_RAMSTAGE)</span><br><span style="color: hsl(120, 100%, 40%);">+ rom_fdt = (const void *)read_csr(mscratch);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> main();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23797">change 23797</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658 </div>
<div style="display:none"> Gerrit-Change-Number: 23797 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>