<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23780">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/cavium: Clean bootblock<br><br>Get rid of unused bootblock stuff.<br><br>Change-Id: I9900848f8b69e3bd391ae99ed706edc4b1a1b922<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/soc/cavium/cn81xx/bootblock.c<br>1 file changed, 3 insertions(+), 70 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/23780/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/cavium/cn81xx/bootblock.c b/src/soc/cavium/cn81xx/bootblock.c</span><br><span>index 66fb98c..d832804 100644</span><br><span>--- a/src/soc/cavium/cn81xx/bootblock.c</span><br><span>+++ b/src/soc/cavium/cn81xx/bootblock.c</span><br><span>@@ -10,84 +10,17 @@</span><br><span> #include <commonlib/helpers.h></span><br><span> #include <soc/bootblock.h></span><br><span> #include <soc/asm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/clock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/l2c.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/mmu_operations.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/sdram.h></span><br><span> #include <soc/sysreg.h></span><br><span> #include <soc/timer.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h>      /* FIXME: for debug prints */</span><br><span style="color: hsl(0, 100%, 40%);">-#include <delay.h>           /* FIXME: for debug prints */</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/exception.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <program_loading.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <timestamp.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void init_sysreg(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">-    if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS1_X))</span><br><span style="color: hsl(0, 100%, 40%);">-    {</span><br><span style="color: hsl(0, 100%, 40%);">-        bdk_ap_cvmctl_el1_t cvmctl_el1;</span><br><span style="color: hsl(0, 100%, 40%);">-        BDK_MRS(s3_0_c11_c0_0, cvmctl_el1.u);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-        /* Errara (AP-22934) CIM module has incorrect conditional clock */</span><br><span style="color: hsl(0, 100%, 40%);">-        if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS1_0))</span><br><span style="color: hsl(0, 100%, 40%);">-            cvmctl_el1.s.force_issue_clock = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-        /* Errata (AP-22500) GlobalSync request during a multi-cycle ATOMIC</span><br><span style="color: hsl(0, 100%, 40%);">-           stalls forever */</span><br><span style="color: hsl(0, 100%, 40%);">-        /* Disable compare and swap on CN88XX pass 1.x */</span><br><span style="color: hsl(0, 100%, 40%);">-        cvmctl_el1.s.disable_casp = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-        cvmctl_el1.s.disable_cas = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-        /* (AP-26147) Event register may not be set */</span><br><span style="color: hsl(0, 100%, 40%);">-        cvmctl_el1.s.disable_wfe = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-        BDK_MSR(s3_0_c11_c0_0, cvmctl_el1.u);</span><br><span style="color: hsl(0, 100%, 40%);">-    }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-    /* Bug #27499 - ISB not flushing the pipeline after a TLBI */</span><br><span style="color: hsl(0, 100%, 40%);">-    if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))</span><br><span style="color: hsl(0, 100%, 40%);">-    {</span><br><span style="color: hsl(0, 100%, 40%);">-        bdk_ap_cvmctl_el1_t cvmctl_el1;</span><br><span style="color: hsl(0, 100%, 40%);">-        BDK_MRS(s3_0_c11_c0_0, cvmctl_el1.u);</span><br><span style="color: hsl(0, 100%, 40%);">-        cvmctl_el1.s.isb_flush = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-        BDK_MSR(s3_0_c11_c0_0, cvmctl_el1.u);</span><br><span style="color: hsl(0, 100%, 40%);">-    }</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">-    /* The defaults for write buffer timeouts are poor */</span><br><span style="color: hsl(0, 100%, 40%);">-    bdk_ap_cvmmemctl0_el1_t cvmmemctl0_el1;</span><br><span style="color: hsl(0, 100%, 40%);">-    BDK_MRS(s3_0_c11_c0_4, cvmmemctl0_el1.u);</span><br><span style="color: hsl(0, 100%, 40%);">-    cvmmemctl0_el1.s.wbftonshena = 1; /* NSH has 2^18 timeout. All BDK mem is NSH */</span><br><span style="color: hsl(0, 100%, 40%);">-    cvmmemctl0_el1.s.wbftomrgclrena = 1; /* Reset timer on merge. Hardware default is brain dead */</span><br><span style="color: hsl(0, 100%, 40%);">-    /* Errata (AP-27388) Flavors of DMB not stalling on subsequent LD */</span><br><span style="color: hsl(0, 100%, 40%);">-    if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X))</span><br><span style="color: hsl(0, 100%, 40%);">-        cvmmemctl0_el1.s.dmbstallforce = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-    BDK_MSR(s3_0_c11_c0_4, cvmmemctl0_el1.u);</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span style="color: hsl(120, 100%, 40%);">+        /* The defaults for write buffer timeouts are poor */</span><br><span>        u64 cvmmemctl0;</span><br><span>      BDK_MRS(s3_0_c11_c0_4, cvmmemctl0);</span><br><span style="color: hsl(0, 100%, 40%);">-     cvmmemctl0 |= AP_CVMMEMCTL0_EL1_WBFTONSHENA | AP_CVMMEMCTL0_EL1_WBFTOMRGCLRENA;</span><br><span style="color: hsl(0, 100%, 40%);">- /* see BDK for errata AP-27388 workaround on CN88xx */</span><br><span style="color: hsl(120, 100%, 40%);">+        cvmmemctl0 |= AP_CVMMEMCTL0_EL1_WBFTONSHENA |</span><br><span style="color: hsl(120, 100%, 40%);">+         AP_CVMMEMCTL0_EL1_WBFTOMRGCLRENA;</span><br><span>    BDK_MSR(s3_0_c11_c0_4, cvmmemctl0);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#if 0</span><br><span style="color: hsl(0, 100%, 40%);">-    /* Enable LMTST and IOATOMIC on CN83XX */</span><br><span style="color: hsl(0, 100%, 40%);">-    if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) || CAVIUM_IS_MODEL(CAVIUM_CN93XX))</span><br><span style="color: hsl(0, 100%, 40%);">-    {</span><br><span style="color: hsl(0, 100%, 40%);">-        bdk_ap_cvmmemctl1_el1_t cvmmemctl1_el1;</span><br><span style="color: hsl(0, 100%, 40%);">-        BDK_MRS(s3_0_c11_c0_5, cvmmemctl1_el1.u);</span><br><span style="color: hsl(0, 100%, 40%);">-        cvmmemctl1_el1.s.lmtstena = 1;</span><br><span style="color: hsl(0, 100%, 40%);">-        cvmmemctl1_el1.s.ioatomicena = 1; // pko _OP_OPEN/CLOSE/QUERY needs that</span><br><span style="color: hsl(0, 100%, 40%);">-        BDK_MSR(s3_0_c11_c0_5, cvmmemctl1_el1.u);</span><br><span style="color: hsl(0, 100%, 40%);">-    }</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span> }</span><br><span> </span><br><span> void bootblock_soc_early_init(void)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23780">change 23780</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23780"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9900848f8b69e3bd391ae99ed706edc4b1a1b922 </div>
<div style="display:none"> Gerrit-Change-Number: 23780 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>