<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/23786">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/romstage.c: Fix AGESA warning<br><br>AmdInitPost returns AGESA_WARNING. This is because AGESA by default<br>enables bank interleaving, while the HW does not meet the requirements<br>for it. After some investigation, it was found that AGESA was really<br>checking rank.<br><br>Using the new rank function, disable bank interleave if the number of<br>ranks is odd.<br><br>BUG=b:73118857<br>TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost()<br>returned AGESA_SUCCESS".<br><br>Change-Id: Id8a2a3bc927f87e91d30971b512fac12230aaad7<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/romstage.c<br>1 file changed, 3 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23786/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c</span><br><span>index 351a266..2488ef9 100644</span><br><span>--- a/src/soc/amd/stoneyridge/romstage.c</span><br><span>+++ b/src/soc/amd/stoneyridge/romstage.c</span><br><span>@@ -176,7 +176,9 @@</span><br><span> </span><br><span>         cfg = dev->chip_info;</span><br><span>     uint8_t ranks = get_total_ranks(cfg);</span><br><span style="color: hsl(0, 100%, 40%);">-   printk(BIOS_SPEW, "Ranks %d\n", ranks);</span><br><span style="color: hsl(120, 100%, 40%);">+     /* If the number of ranks is odd, disable interleaving */</span><br><span style="color: hsl(120, 100%, 40%);">+     if (ranks & 1)</span><br><span style="color: hsl(120, 100%, 40%);">+            PostParams->MemConfig.EnableBankIntlv = FALSE;</span><br><span> </span><br><span>        PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/23786">change 23786</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/23786"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id8a2a3bc927f87e91d30971b512fac12230aaad7 </div>
<div style="display:none"> Gerrit-Change-Number: 23786 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>